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.....Synthesizing signals

 
 
knight knight is offline
Junior Member
Join Date: Dec 2007
Posts: 4
 
      12-22-2007
Hi... 2 questionz...

Que 1...

1) we declare a signal
2) not initialising any value to it ( on reset or any other way)
3) we are processing it in code

will it take default any default value as per the compiler or
will it always be in uninitialised state ( or in unknown state ) ???

Example :-

...
signal x;
...
...
x <= x and p; ( x is not initialised any value and p is '1' )
...
...

How this is synthesised...? and what will be the synthesis o/p ..?



Que 2...

...
signal x :std_logic := '1';
...
how this is synthsized ....?



thanks
knight
 
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