Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Simulation of Xilinx Rocket IO Instance

Reply
Thread Tools

Simulation of Xilinx Rocket IO Instance

 
 
kedarpapte@gmail.com
Guest
Posts: n/a
 
      03-06-2006
Hello All,

I want to use Xilinx v2p or v4 rocket IOs in one of my designs.
right now I am using Xilinx webpack 8.1 and modelsim se/pe.

can any body tell me that if I generate a rocket IO instance (without
8b10b and crc) as a simple serdes How do I simulate it...?

Does the Rocket IO Instance has any output pins for PLL Locked
signals...?

I am trying to simulate a transmitter by a simple test bench as to
provide reset, clock and 8-bit parallel data, but nothing is coming out
on serial tx pin.

Please guide me .
Thanks in advance.

Regards,
Kedar

 
Reply With Quote
 
 
 
 
beeraka@gmail.com
Guest
Posts: n/a
 
      03-07-2006
Hi Kedar,
I was able to simulate stuff for one of the boards that
we use based on this reference design ..

http://www.digilentinc.com/Data/Prod...v2p_aurora.zip

--
Parag

 
Reply With Quote
 
 
 
 
kedarpapte@gmail.com
Guest
Posts: n/a
 
      03-07-2006
thanks for the zip file I will try and run that simulation
but when I open the project in ISE I am not able to see some of the
instanciated parts like
aurora_module_i_1
standard_cc_module_i_1
aurora_module_i_2
standard_cc_module_i_2

from where I should add this...?

please help me

Thanks & Regards
Kedar

 
Reply With Quote
 
Paul Hartke
Guest
Posts: n/a
 
      03-07-2006
You need to generate these files from Coregen. It is explained in the
Aurora_QuickStart.pdf document in the zip file.

Paul

http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
>
> thanks for the zip file I will try and run that simulation
> but when I open the project in ISE I am not able to see some of the
> instanciated parts like
> aurora_module_i_1
> standard_cc_module_i_1
> aurora_module_i_2
> standard_cc_module_i_2
>
> from where I should add this...?
>
> please help me
>
> Thanks & Regards
> Kedar

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Simulation of VHDL in xilinx from a C program? jesse lackey VHDL 3 05-25-2007 10:41 AM
How to compile Xilinx Timing-Simulation library SIMPRIM under NC-Sim uvbaz VHDL 2 10-27-2006 07:23 AM
Error in FIFO Simulation ISE Xilinx nfirtaps VHDL 1 08-31-2006 05:17 PM
Simulation of rocket IO in virtex 2 pro Stephen Lohning VHDL 3 05-24-2005 07:22 AM
post PAR simulation with Xilinx Project Navigator: how? ra VHDL 0 08-03-2004 06:47 PM



Advertisments