Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > std_logic_vector signals in sensitivity list process

Reply
Thread Tools

std_logic_vector signals in sensitivity list process

 
 
Steven Kauffmann
Guest
Posts: n/a
 
      12-21-2007
Hello all,

I have some questions about how to use std_logic_vector signals in the
sensitivity list of a process.

First of all, is the sensitivity list like a comparator in hardware
and does it continuously checks if the value changes? Or is the
sensitivity list only important when simulating the design?

If I use a std_logic_vector signal in the sensitivity list, are all
the bits of this signal compared or is only one bit(MSB of LSB) used?

Is there a difference between those two sensitivity lists?

process(port_a(4 downto 0))
begin
-- do something
end process

process(port_a(3), port_a(2), port_a(1), port_a(0))
begin
-- do something
end process

Regards

Steven



 
Reply With Quote
 
 
 
 
paragon.john@gmail.com
Guest
Posts: n/a
 
      12-21-2007
Steven,

Sensitivity lists are relevant only in simulation. A synthesizer
should warn you, however, if you have any signals missing from your
sensitivity list, so as to let you know that you may have a simulation/
synthesis mismatch.

I believe your two examples would be dealt with in the same way, you
could also just do the following...

process(port_a)
begin
-- do something
end process

Regards,
John

On Dec 21, 7:42 am, Steven Kauffmann <(E-Mail Removed)>
wrote:
> Hello all,
>
> I have some questions about how to use std_logic_vector signals in the
> sensitivity list of a process.
>
> First of all, is the sensitivity list like a comparator in hardware
> and does it continuously checks if the value changes? Or is the
> sensitivity list only important when simulating the design?
>
> If I use a std_logic_vector signal in the sensitivity list, are all
> the bits of this signal compared or is only one bit(MSB of LSB) used?
>
> Is there a difference between those two sensitivity lists?
>
> process(port_a(4 downto 0))
> begin
> -- do something
> end process
>
> process(port_a(3), port_a(2), port_a(1), port_a(0))
> begin
> -- do something
> end process
>
> Regards
>
> Steven


 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      12-22-2007
Steven Kauffmann wrote:

> Is there a difference between those two sensitivity lists?


Yes, one has 5 bits and the other has 4 bits


Note that the use of asynchronous processes is usually optional.
Using a synchronous process template eliminates concerns about
sensitivity lists and many other things.
__
sync_template : process(reset, clock) is
-- declarations here
begin
if reset = '1' then
init_regs;
elsif rising_edge(clock) then
update_regs;
end if;
update_ports;
end process sync_template;
__
-- Mike Treseler
 
Reply With Quote
 
Steven Kauffmann
Guest
Posts: n/a
 
      12-24-2007
On Dec 21, 3:49 pm, (E-Mail Removed) wrote:
> Steven,
>
> Sensitivity lists are relevant only in simulation. A synthesizer
> should warn you, however, if you have any signals missing from your
> sensitivity list, so as to let you know that you may have a simulation/
> synthesis mismatch.


So this means that the process below is not working when it's
implemented in hardware this because the sensitivity list is ignored
and so the process will never be updated?

process(port_a)
begin
-- do something
end process;

> I believe your two examples would be dealt with in the same way, you
> could also just do the following...
>
> process(port_a)
> begin
> -- do something
> end process
>
> Regards,
> John
>
> On Dec 21, 7:42 am, Steven Kauffmann <(E-Mail Removed)>
> wrote:
>
> > Hello all,

>
> > I have some questions about how to use std_logic_vector signals in the
> > sensitivity list of a process.

>
> > First of all, is the sensitivity list like a comparator in hardware
> > and does it continuously checks if the value changes? Or is the
> > sensitivity list only important when simulating the design?

>
> > If I use a std_logic_vector signal in the sensitivity list, are all
> > the bits of this signal compared or is only one bit(MSB of LSB) used?

>
> > Is there a difference between those two sensitivity lists?

>
> > process(port_a(4 downto 0))
> > begin
> > -- do something
> > end process

>
> > process(port_a(3), port_a(2), port_a(1), port_a(0))
> > begin
> > -- do something
> > end process

>
> > Regards

>
> > Steven


 
Reply With Quote
 
kennheinrich@sympatico.ca
Guest
Posts: n/a
 
      12-24-2007
On Dec 24, 3:10 am, Steven Kauffmann <(E-Mail Removed)>
wrote:

> So this means that the process below is not working when it's
> implemented in hardware this because the sensitivity list is ignored
> and so the process will never be updated?
>
> process(port_a)
> begin
> -- do something
> end process;
>


Not quite. VHDL is fundamentally a simulation language, which, when
written using certain common styles, allow it to be used as a source
language for hardware synthesis. This code really could have two ways
to interpret it: one in a simulation environment, which is exactly
what the official language definition explains, and one interpretation
as a hardware description, which is fuzzier. The idea behind using
certain common coding styles is to make sure the behaviour of your
code in simulation and synthesis are the same. That's what's meant by
"synthesis/simulation mismatch".

For simulation purposes, a process with a sensitivity list will run
exactly once at initialization (although in no particular order w.r.t.
other processes' initialization steps), and when the signal changes.
If you specify the wrong sensitivity list by accident, your process
won't respond as you expect (either ignoring events on the signal you
wanted to use, or firing at apparently random other times).

Generally, if you just want a process that responds asynchronously,
immediately, to a set of signals, (like if you're writing a simple
logic gate or an asynchronous memory read), you can skip the
sensitivity list altogether and the compiler will figure out the right
sensitivity list automatically, by looking at every signal that gets
read in the process. You want to either specify every signal correctly
or specify no signals at all in the sensitivity list. Otherwise
there's a good chance that you messed up.

Your question about "comparator in hardware" doesn't quite catch the
idea. If you wanted to follow this analogy, think of a process as
specifying some kind of piece of logic that might be a mixture of
clocked and combinatorial. The sensitivity list defines those inputs
which, if they have an event on them, may cause the output to change.
This means that those signals are either directly connected to the
circuit output through gates, or are used as clock input edges. (This
is admittedly a sloppy analogy.)

When you want to write something behind a clocked register (like a
counter, state machine, etc), you typically _only_ specify the clock
signal in the sensitivity list. Then you put the entire body of the
process inside an "if rising_edge(clk)..." statement. The combination
of these two things tells the synthesizer to generate the
combinatorial logic specified inside the "if" statement, with a flop
on each output signal you assign to. This again, is admittedly a
sloppy description of the synthesis process

If you write processes that don't follow one of these three styles
(clocked, combinatorial with no sensitivity, or combinatorial with
complete sensitivity), you're either doing the wrong thing (if you're
a beginner) or are trying to do something fancy (if you're a more
advanced user). If you're trying to be fancy as an advanced user,
there's still a good chance you're wrong, at least the first few
times

And so as to make sure to answer your last question:

process(port_a)
blah blah...

will run in simulation at initialization and when any subelement on
port_a (or port_a in its entirety) changes. In hardware, as long as
port_a is the only signal you look at inside your process, you should
be generating a simple combinatorial function of port_a. If
"blah_blah_bah" reads signals _other_ than port_a, or doesn't have the
complete sensitivity list (as in the 4 vs 5 signal discrepancy Mike
pointed out), you're most likely generating something which you didn't
want, regardless of whether you're simulating or synthesizing.

Hope this helps,

- Kenn

 
Reply With Quote
 
Dwayne Dilbeck
Guest
Posts: n/a
 
      01-02-2008
The way the sensitivity list is synthesized is going to dependon the tool
being used. Aside from an extra bit in the sensitivity list the two would
function the same. But synthesis could be completely different. In our
synthesis tool the "sensitivity list" is completely ignored in some
situations. We actually have a coding guide for our tool that states how
the sensitivity list will be synthesized based on the code inside the block.

Check to see if your synthesis tool has a coding guide for using sensitivity
lists.


"Steven Kauffmann" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> Hello all,
>
> I have some questions about how to use std_logic_vector signals in the
> sensitivity list of a process.
>
> First of all, is the sensitivity list like a comparator in hardware
> and does it continuously checks if the value changes? Or is the
> sensitivity list only important when simulating the design?
>
> If I use a std_logic_vector signal in the sensitivity list, are all
> the bits of this signal compared or is only one bit(MSB of LSB) used?
>
> Is there a difference between those two sensitivity lists?
>
> process(port_a(4 downto 0))
> begin
> -- do something
> end process
>
> process(port_a(3), port_a(2), port_a(1), port_a(0))
> begin
> -- do something
> end process
>
> Regards
>
> Steven
>
>
>



 
Reply With Quote
 
KJ
Guest
Posts: n/a
 
      01-02-2008

"Dwayne Dilbeck" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> The way the sensitivity list is synthesized is going to dependon the tool
> being used.

The only 'tool dependency' would be because the tool does not conform to the
VHDL LRM.

> Aside from an extra bit in the sensitivity list the two would function the
> same.

Well, they would likely synthesize to the exact same thing....but the
synthesized result would differ from that of simulation because of the
different signals in the sensitivity list. The 'correct' one would be the
simulation result, the synthesized result would be wrong.

> But synthesis could be completely different. In our synthesis tool the
> "sensitivity list" is completely ignored in some situations.

Bragging about LRM non-compliance??

> We actually have a coding guide for our tool that states how the
> sensitivity list will be synthesized based on the code inside the block.
>

I prefer the approved standards myself as opposed to a vendor's shortcuts.

> Check to see if your synthesis tool has a coding guide for using
> sensitivity lists.
>

Check the LRM instead.

I admit that I do prefer the usual synthesizer's ignoring of the sensitivity
list and putting up a warning to indicate when I have an incomplete list or
a signal that does not belong but that not being the standard, but I MUCH
MORE strongly prefer simulation results to match synthesized results.

But by not using processes other than clocked ones where 'clock' (or 'clock'
and 'reset') is the extent of the sensitivity list means I normally don't
even have to bother with this issue at all.

Kevin Jennings


 
Reply With Quote
 
Dwayne Dilbeck
Guest
Posts: n/a
 
      01-03-2008
> Bragging about LRM non-compliance??
Uhm...NO....I hate non conformance, but that is a battle I lost a long time
ago.
When ever we have non-conformance it is caused by one of three issues. 1)
We screed up, 2) A competitor screwed up and we now have to match thier
functionality, or 3) the customer requested we have an alterante path that
is not compliant.

The comment to check his vendors RTL style guide was to address items 2 and
3. If his problem is due to item #1, then it has to be fixed. But cases 2
and 3 are more common in my experience. Granted...My company will break LRM
for any customer that waves enough money at us.(As will most EDA companies)
It just drives me crazy when we make non-conformance a default option
becuase a customer wants it.

I have actually seen two seperate companies want LRM non conformance, but
implemented differently. Niether wanted to use a command line switch to
activate it. Both were holding up big money deals until they got thier
enhancement. Nasty.


 
Reply With Quote
 
Andy
Guest
Posts: n/a
 
      01-03-2008
On Jan 2, 5:31 pm, "KJ" <(E-Mail Removed)> wrote:
> "Dwayne Dilbeck" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed)...> The way the sensitivity list is synthesized is going to dependon the tool
> > being used.

>
> The only 'tool dependency' would be because the tool does not conform to the
> VHDL LRM.
>
> > Aside from an extra bit in the sensitivity list the two would function the
> > same.

>
> Well, they would likely synthesize to the exact same thing....but the
> synthesized result would differ from that of simulation because of the
> different signals in the sensitivity list. The 'correct' one would be the
> simulation result, the synthesized result would be wrong.
>
> > But synthesis could be completely different. In our synthesis tool the
> > "sensitivity list" is completely ignored in some situations.

>
> Bragging about LRM non-compliance??
>
> > We actually have a coding guide for our tool that states how the
> > sensitivity list will be synthesized based on the code inside the block.

>
> I prefer the approved standards myself as opposed to a vendor's shortcuts.
>
> > Check to see if your synthesis tool has a coding guide for using
> > sensitivity lists.

>
> Check the LRM instead.
>
> I admit that I do prefer the usual synthesizer's ignoring of the sensitivity
> list and putting up a warning to indicate when I have an incomplete list or
> a signal that does not belong but that not being the standard, but I MUCH
> MORE strongly prefer simulation results to match synthesized results.
>
> But by not using processes other than clocked ones where 'clock' (or 'clock'
> and 'reset') is the extent of the sensitivity list means I normally don't
> even have to bother with this issue at all.
>
> Kevin Jennings


Let's face it, the 800 lb gorilla (Synopsys) decided a long time ago
that they were going to ignore sensitivity lists in synthesis, and
everyone else followed suit, because customers (waiving money) wanted
tools that work "just like Synopsys", instead of "just like the LRM".
Ditto for std_logic_arith, etc.

It really galls me that when we requested that Synopsys add a command
line feature (like modelsim) to only compile certain design unit types
found in the file(s) (i.e. only architectures, etc.). They replied
that the LRM prohibited such a practice! One could argue that the LRM
prohibits out of order compilation of units within one file (an ncsim
and modelsim option), and I seriously doubt that interpretation was
intended by the authors, but it says nothing requiring compiling every
design unit in a file.

Andy
 
Reply With Quote
 
Dwayne Dilbeck
Guest
Posts: n/a
 
      01-03-2008
> Bragging about LRM non-compliance??
Uhm...NO....I hate non conformance, but that is a battle I lost a long time
ago.
When ever we have non-conformance it is caused by one of three issues. 1)
We screed up, 2) A competitor screwed up and we now have to match thier
functionality, or 3) the customer requested we have an alterante path that
is not compliant.

The comment to check his vendors RTL style guide was to address items 2 and
3. If his problem is due to item #1, then it has to be fixed. But cases 2
and 3 are more common in my experience. Granted...My company will break LRM
for any customer that waves enough money at us.(As will most EDA companies)
It just drives me crazy when we make non-conformance a default option
becuase a customer wants it.

I have actually seen two seperate companies want LRM non conformance, but
implemented differently. Niether wanted to use a command line switch to
activate it. Both were holding up big money deals until they got thier
enhancement. Nasty.

"KJ" <(E-Mail Removed)> wrote in message
news9Vej.2718$6%(E-Mail Removed)...
>
> "Dwayne Dilbeck" <(E-Mail Removed)> wrote in message
> news:(E-Mail Removed)...
>> The way the sensitivity list is synthesized is going to dependon the tool
>> being used.

> The only 'tool dependency' would be because the tool does not conform to
> the VHDL LRM.
>
>> Aside from an extra bit in the sensitivity list the two would function
>> the same.

> Well, they would likely synthesize to the exact same thing....but the
> synthesized result would differ from that of simulation because of the
> different signals in the sensitivity list. The 'correct' one would be the
> simulation result, the synthesized result would be wrong.
>
>> But synthesis could be completely different. In our synthesis tool the
>> "sensitivity list" is completely ignored in some situations.

> Bragging about LRM non-compliance??
>
>> We actually have a coding guide for our tool that states how the
>> sensitivity list will be synthesized based on the code inside the block.
>>

> I prefer the approved standards myself as opposed to a vendor's shortcuts.
>
>> Check to see if your synthesis tool has a coding guide for using
>> sensitivity lists.
>>

> Check the LRM instead.
>
> I admit that I do prefer the usual synthesizer's ignoring of the
> sensitivity list and putting up a warning to indicate when I have an
> incomplete list or a signal that does not belong but that not being the
> standard, but I MUCH MORE strongly prefer simulation results to match
> synthesized results.
>
> But by not using processes other than clocked ones where 'clock' (or
> 'clock' and 'reset') is the extent of the sensitivity list means I
> normally don't even have to bother with this issue at all.
>
> Kevin Jennings
>
>



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Interface between floating-point and std_logic_vector signals. Rain VHDL 4 04-30-2008 04:16 PM
inout std_logic_vector to array of std_logic_vector of generic length conversion... Thomas Rouam VHDL 6 11-09-2007 11:49 AM
The following signals are missing in the process sensitivity list antonio bergnoli VHDL 5 12-18-2005 08:16 PM
redundant signals in sensitivity list? Neil Zanella VHDL 15 12-18-2003 04:03 AM
Are all the signals read in the process should appear in the sensitivity list of the process? walala VHDL 3 09-09-2003 07:47 AM



Advertisments