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I am looking for a reality check. I have 10 years experience doing
software verification on EDA tools, in particular hardware emulators, System
Verilog, and VHDL. When looking at some job ads I see "required 6+ years
ASIC verification experience", can any of my 10 years experience be
converted? I firmly believe with the continued use of RTL coding for
designs, SW quality methods can be applied. Am I deluding myself?

All other requirements like "strong Verilog, Perl, and C++ programming
skills" or "emulation experience" I meet. I am not sure how my years
verifying synthesis and emulation tools can be translated for ASIC
verification experience.

Dwayne,

I would say "go for it."

Don't worry about "converting" experience: what they are asking for
probably does not exist in any one human being, anyway.

ASIC verification is 100% software tool exercises before silicon
arrives. Once silicon arrives, ASIC verification takes more physical
forms (bench, tester, system, etc. testing).

"Verification" by IC designers is probably 95% of what they do (maybe
even 98%); whether it is verilog or VHDL test benches, c, or c++ models,
spice level simulations, or clever combinations of all of the above.

The same methods used to check software quality are used to check
hardware quality: checklists of what tests must be done, and under what
conditions and stimuli, regression testing against past known issues,
and so forth.

I am surprised not see that they require a particular scripting
language, as that is part of any verification "toolkit" (to automate as
much of the drudgery as possible).

Austin


Dwayne Dilbeck wrote:
> I am looking for a reality check. I have 10 years experience doing
> software verification on EDA tools, in particular hardware emulators, System
> Verilog, and VHDL. When looking at some job ads I see "required 6+ years
> ASIC verification experience", can any of my 10 years experience be
> converted? I firmly believe with the continued use of RTL coding for
> designs, SW quality methods can be applied. Am I deluding myself?
>
> All other requirements like "strong Verilog, Perl, and C++ programming
> skills" or "emulation experience" I meet. I am not sure how my years
> verifying synthesis and emulation tools can be translated for ASIC
> verification experience.
>
>

Thanks. I haven't been in the job market for 10 years since I got out of
college. Thus, I wanted to verify my thought process.

"austin" <> wrote in message
news:fkbuug$...
> Dwayne,
>
> I would say "go for it."
>
> Don't worry about "converting" experience: what they are asking for
> probably does not exist in any one human being, anyway.
>
> ASIC verification is 100% software tool exercises before silicon
> arrives. Once silicon arrives, ASIC verification takes more physical
> forms (bench, tester, system, etc. testing).
>
> "Verification" by IC designers is probably 95% of what they do (maybe
> even 98%); whether it is verilog or VHDL test benches, c, or c++ models,
> spice level simulations, or clever combinations of all of the above.
>
> The same methods used to check software quality are used to check
> hardware quality: checklists of what tests must be done, and under what
> conditions and stimuli, regression testing against past known issues,
> and so forth.
>
> I am surprised not see that they require a particular scripting
> language, as that is part of any verification "toolkit" (to automate as
> much of the drudgery as possible).
>
> Austin
>
>
> Dwayne Dilbeck wrote:
>> I am looking for a reality check. I have 10 years experience doing
>> software verification on EDA tools, in particular hardware emulators,
>> System
>> Verilog, and VHDL. When looking at some job ads I see "required 6+
>> years
>> ASIC verification experience", can any of my 10 years experience be
>> converted? I firmly believe with the continued use of RTL coding for
>> designs, SW quality methods can be applied. Am I deluding myself?
>>
>> All other requirements like "strong Verilog, Perl, and C++ programming
>> skills" or "emulation experience" I meet. I am not sure how my years
>> verifying synthesis and emulation tools can be translated for ASIC
>> verification experience.
>>
>>

"austin" <> wrote in message
news:fkbuug$...
> Dwayne,
>
> I would say "go for it."
>
> Don't worry about "converting" experience: what they are asking for
> probably does not exist in any one human being, anyway.
>
> ASIC verification is 100% software tool exercises before silicon
> arrives. Once silicon arrives, ASIC verification takes more physical
> forms (bench, tester, system, etc. testing).
>
> "Verification" by IC designers is probably 95% of what they do (maybe
> even 98%); whether it is verilog or VHDL test benches, c, or c++ models,
> spice level simulations, or clever combinations of all of the above.
>
> The same methods used to check software quality are used to check
> hardware quality: checklists of what tests must be done, and under what
> conditions and stimuli, regression testing against past known issues,
> and so forth.
>
> I am surprised not see that they require a particular scripting
> language, as that is part of any verification "toolkit" (to automate as
> much of the drudgery as possible).
>
> Austin

I agree with Austin, just go for it, in the worst case you come out with
some extra experience on how to handle a job interview.

I would however advise you to have a quick google on some of the
verification techniques (if you don't already know them) such as functional
coverage, assertions based verification, constraint random and transaction
level modelling, nothing fancy just understand their advantages and
disadvantages and some of the languages they use. Having said that I suspect
a lot of verfication is still done using nothing more than a VHDL/Verilog
testbench in a similar trend to some FPGA engineers just loading the design
on the board and see if it works

Hans
www.ht-lab.com

> I would however advise you to have a quick google on some of the
> verification techniques (if you don't already know them) such as
> functional coverage, assertions based verification, constraint random and
> transaction level modelling, nothing fancy just understand their
> advantages and disadvantages and some of the languages they use. Having
> said that I suspect a lot of verfication is still done using nothing more
> than a VHDL/Verilog testbench in a similar trend to some FPGA engineers
> just loading the design on the board and see if it works

Thank you Hans for the feedback. I am starting to have a very confident
feeling. Especially when the areas you mentioned to google turned out to be
areas I am very familiar with. I have been testing those areas in our EDA
tools, I have a very firm grasp on those concepts and where they fall apart
atleast for one set of EDA tools.

Thank you everyone for the feedback the resume's are going out today.