VCS simulation for VHDL DUT and Verilog test bench

kartikey

Junior Member

Join Date: Dec 2007

Posts: 1

12-18-2007

I have VHDL package in file1.vhd. This package is used in DUT file2.vhd. Test bench to test this DUT is developed in verilog (file3.v). I need to simulate it using vcs mix mode simulation. If possible, someone please show me the steps to do the process for vcs-mx.

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