Ben,

This too is due to be fixed in the next revision of

VHDL. This revision will first be standardized by

Accellera (the group working on the revisions) in

July of 2006.

is_equal <= foo ?= bar ;

in addition:

Reg1Sel <= BlkSel and (Addr ?= REG1_ADDR_LOC) ;

Please let your vendor know that you want them to

implement this.

Cheers,

Jim

> -- In your package of useful functions:

>

> function btsl(x : boolean) return std_logic is

> -- btsl == Boolean To Standard Logic

> begin if x then return '1'; else return '0'; end if;

> end btsl;

>

>

> -- In your design code:

>

> process(...)

> begin

>

> is_equal <= btsl(foo=bar);

>

> end process;

>

> That is fairly short...

>

> -Ben-

>

>
--

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Jim Lewis

Director of Training (E-Mail Removed)

SynthWorks Design Inc.

http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~