Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > need help... VHDL Variable problem...

Reply
Thread Tools

need help... VHDL Variable problem...

 
 
elements_me elements_me is offline
Junior Member
Join Date: Dec 2007
Posts: 2
 
      12-16-2007
my variable (ADDER) value don't know y change to some others value @@... can everybody help me... my codes is below...

ENTITY neo IS
PORT ( I_10 , I_20 , I_50 : IN STD_LOGIC;
X : IN STD_LOGIC;
clk : IN STD_LOGIC;
END neo;

ARCHITECTURE beha OF neo IS

TYPE states IS ( SR , S0 );
SIGNAL state : states;
SIGNAL CD : STD_LOGIC_VECTOR ( 5 DOWNTO 0 );
SIGNAL E : STD_LOGIC;
SIGNAL EX : STD_LOGIC;
SIGNAL RD1 , RD2 : STD_LOGIC :='0' ;
SIGNAL S_ADDER : INTEGER range 0 to 140 := 0;
SIGNAL ID : STD_LOGIC_VECTOR ( 2 DOWNTO 0 );

BEGIN

ID <= I_50 & I_20 & I_10;
CD <= R & E & X & S & EX;

PROCESS ( clk , state , X , I_10 , I_20 , I_50 )
VARIABLE A_A , A_B , A_C , A_10 , A_20 , A_50 : INTEGER;
VARIABLE ADDER : INTEGER := 0;
BEGIN
IF rising_edge ( clk ) THEN
CASE state IS
WHEN SR =>
IF ( RD1 = '1' ) THEN
ADDER := 0;
T_ADDER := 0;
A_10 := 100;
A_20 := 100;
A_50 := 100;
E <= '0';
EX <= '0';
RD2 <= '1';
END IF;

WHEN S0 =>
IF ( ADDER < 100 ) THEN
CASE ID IS
WHEN "001" =>
ADDER := ADDER + 10;
WHEN "010" =>
ADDER := ADDER + 20;
WHEN "100" =>
ADDER := ADDER + 50;
WHEN OTHERS =>
NULL;
END CASE;
END IF;

state SR will go to state S0 after those value reset ( no show in the code ) ... the problem is the value of ADDER,,, let's said I_50 = '1'... the ID = "100"... and ADDER should be 50... but the face is when i see the timing diagram... the adder value is not 50... it is something else... like 32 like that... how come ??? help... really take me long time to check it le...
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
"Variable variable name" or "variable lvalue" mfglinux Python 11 09-12-2007 03:08 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
multiD-vhdl: Multi Dimensional Arrays (allowing generics on each dimension) for VHDL (including ports) albert.neu@gmail.com VHDL 2 03-21-2006 04:05 PM
How do I scope a variable if the variable name contains a variable? David Filmer Perl Misc 19 05-21-2004 03:55 PM
what's the difference between VHDL 93 CONCATENATION and VHDL 87 CONCATENATION? walala VHDL 3 09-18-2003 04:17 AM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57