Velocity Reviews > VHDL > portable (VHDL) vs. non-portable (altera LPM) approaches to signed computations

# portable (VHDL) vs. non-portable (altera LPM) approaches to signed computations

Eli Bendersky
Guest
Posts: n/a

 03-01-2006
Hello All,

I have to do some signed arithmetic computations in my code and I'm
wondering which is the better approach. The operations I need are
addition, subtraction, multiplication and comparison. The two choices I
have are:

1) Use the VHDL signed arithmetic library. The advantage of this method
is its portability
2) Use the Altera LPMs (megafunctions). These are not portable, but
rather Altera specific (OTOH, all I need is Altera), but are
recommended by Altera and I can clearly see that they are
synthesizable.

What would you recommend ? Are the VHDL signed arithmetic operations
(especially multiplication) correctly synthesizable on Altera ?

How would you go about writing a computation, of say RMS (square root
excluded) ?

Mike Treseler
Guest
Posts: n/a

 03-01-2006
Eli Bendersky wrote:

> I have to do some signed arithmetic computations in my code and I'm
> wondering which is the better approach. The operations I need are
> addition, subtraction, multiplication and comparison. The two choices I
> have are:
>
> 1) Use the VHDL signed arithmetic library. The advantage of this method
> is its portability

The standard library is numeric_std, not signed:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

> 2) Use the Altera LPMs (megafunctions). These are not portable, but
> rather Altera specific (OTOH, all I need is Altera), but are
> recommended by Altera and I can clearly see that they are
> synthesizable.

Picking out device specific primitives is the job of synthesis.
Altera Quartus 5.1 synthesis is very good, so let it earn it's keep.
I am better off saying n:= n+1; than I am picking out an adder myself.
The code is easier to read and if I change vector widths, it still works.

-- Mike Treseler