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dimmutal dimmutal is offline
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Join Date: Feb 2006
Posts: 1
Hi there,

I would like to know how to enter an input from Simulink to a VHDL model i have.
I have made several simulations but the case here is that my input port of my entity is an array of std_logic_vector. I have used succesfully the Random Number Generator in Simulink as an input to a simple std_logic_vector input port, but i can't find a way to enter an input to an ARRAY of std_logic_vector. Any recommendations?
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