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12-10-2007, 02:34 AM
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full adder example using fpga
Hello group, Does anybody know about an online resource that I can find some samples on how to implement a full adder using LUT? either using Flex10k or any other classical methods? I've started learning FPGA and have done something but need to compare it. Regards, Amit Amit |
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12-10-2007, 02:05 PM
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#2 |
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Posts: n/a
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Re: full adder example using fpga
On Dec 9, 9:34 pm, Amit <amit.ko...@gmail.com> wrote:
> Hello group, > > Does anybody know about an online resource that I can find some > samples on how to implement a full adder using LUT? Google lists about 19000 http://www.google.com/search?hl=en&q=VHDL+full+adder KJ KJ |
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12-11-2007, 03:01 PM
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#3 |
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Posts: n/a
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Re: full adder example using fpga
Amit schrieb:
> Does anybody know about an online resource that I can find some > samples on how to implement a full adder using LUT? either using > Flex10k or any other classical methods? Usually you don't need to think about every single fulladder. Just use result<=a+b; -- all signals are vectors of type signed or unsigned For a single fulladder you could use: signal result : unsigned(1 downto 0); signal a,b,c_in : std_ulogic; signal sum,c_out : std_ulogic; result<=unsigned('0' & a) + unsigned('0' & b) + unsigned('0' & c_in); sum<=result(0); c_out<=result(1); Ralf Ralf Hildebrandt |
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12-12-2007, 03:28 PM
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#4 |
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Re: full adder example using fpga
On Dec 11, 9:01 am, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:
> Amit schrieb: > > > Does anybody know about an online resource that I can find some > > samples on how to implement a full adder using LUT? either using > > Flex10k or any other classical methods? > > Usually you don't need to think about every single fulladder. Just use > result<=a+b; -- all signals are vectors of type signed or unsigned > > For a single fulladder you could use: > > signal result : unsigned(1 downto 0); > signal a,b,c_in : std_ulogic; > signal sum,c_out : std_ulogic; > > result<=unsigned('0' & a) + unsigned('0' & b) + unsigned('0' & c_in); > sum<=result(0); > c_out<=result(1); > > Ralf It's even easier with integers: signal a,b,sum,c_in,c_out : integer range 0 to 1; sum <= (a + b + c_in) mod 2; c_out <= (a + b + c_in) / 2; Andy Andy |
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12-12-2007, 05:44 PM
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#5 |
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Posts: n/a
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Re: full adder example using fpga
Andy wrote:
> It's even easier with integers: Easier still, if I let synthesis wire up the carries  -- Mike Treseler Mike Treseler |
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12-12-2007, 07:59 PM
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#6 |
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Posts: n/a
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Re: full adder example using fpga
On Dec 12, 9:44 am, Mike Treseler <mike_trese...@comcast.net> wrote:
> Andy wrote: > > It's even easier with integers: > > Easier still, if I let synthesis wire up the carries > > -- Mike Treseler Thanks to all, But maybe I didn't ask the question properly or I had to post in a different group (I'm sure doesn't exist). My concern is not regarding VHDL sytnax but trying to understand how to tacking the flow on a Flex10K diagram. I apologize all for this. However, if somebody knows this I will be more than happy to have your help. Regards, Amit Amit |
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