«

Michael Attenborough wrote:

>>Something like
>> IF fast_c generate ...
>> IF not fast_c generate ...
>
> In the case of the RAM model selection, this means changing all the entities
> in the instantiation path so that I can thread a 'generic' value through to
> them - yuck. Possibly an feasible option for the device-under-test
> selection, though - although here, the configuration is fairly simple to
> write, and arguably neater.

After having tried out the idea for synthesis,
I would now say that a special compile script
or separate top entities is less trouble.

Configurations are neater once finished.
However, it can be mind-numbing getting them that way.
The real downside for me is maintaining the components and
entities separately and verifying that the complete
set of tools can understand them.

>>You could assign generic defaults for this
>>case and and just leave out the map.

> That doesn't work, because the default generics (from the RTL entity) are
> not what I want: I want no generics when I am plugging in the gatelevel
> model in place of the RTL. ModelSim gives me an error "Entity does not have
> a generic named xxx" when I try to compile the configuration without a
> generic map. I can define a completely different generic map if I want, but
> I don't know how to specify an empty generic map. An omisssion from the
> language spec?

If the base entity has a generic, it always has some value.
All you can do is leave it alone or map it to some other value.

> As far as I can see, I also can't apply a configuration to anything below a
> directly instantiated entity/architecture in the instantiation tree - is
> this true, or is it that I just don't know the correct syntax to do it?

Direct instances and configurations don't mix.
See the rest of this thread for other discussion.

-- Mike Treseler

Mike Treseler <> writes:

> Configurations are neater once finished.
> However, it can be mind-numbing getting them that way.
> The real downside for me is maintaining the components and
> entities separately and verifying that the complete
> set of tools can understand them.

But Emacs' VHDL-mode can create you a single VHD file with all your
components in it at the click of a mouse

Cheers,
Martin

--

TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

Martin Thompson wrote:

> But Emacs' VHDL-mode can create you a single VHD file with all your
> components in it at the click of a mouse

Yes it can. I do use the vhdl-compose commands for creating
structural top-entities but I keep vhdl-use-direct-instantiation
turned on. If you turn if off, vhdl-mode can make component
declarations for you and collect them in a package.
If you like configurations this is probably the easiest
way to do it. However vhdl-use-direct-instantiation is a
global, not a project setting.

To do a gate sim in vhdl-mode, I define a separate
project directory containing only the synthesis
netlist (.vho) work directory and Makefile.
The testbench and vendor libraries are compiled
in by reference from other directories.
This works fine and keeps my design projects
clean and simple.

-- Mike Treseler