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I have a board on which SRAM is attached to an Altera Cyclone-II FPGA. I
would like to use the SRAM as a FIFO. The memory is capable of running
at 160MHz, the spec for the FIFO is 40MHz, so the SRAM could easily be
cycle-shared between read and write.
I can imagine that this kind of problem is very common, so my question:
Has anybody already written VHDL to control the SRAM in such a way that
it acts like a FIFO? If so, would you be willing to share your design?


--
Dr Joachim Schambach
The University of Texas at Austin
Department of Physics
1 University Station C1600
Austin, Texas 78712-0264, USA
Phone: (512) 471-1303; FAX: (814) 295-5111
e-mail:

Jo Schambach wrote:

> I can imagine that this kind of problem is very common, so my question:
> Has anybody already written VHDL to control the SRAM in such a way that
> it acts like a FIFO? If so, would you be willing to share your design?

A synchronous fifo is just an SRAM that uses
a push or pop counter for write or read addresses.
Here is the guts of a block-ram based design:

begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(push_tail_ptr)) <= data_i; -- raw address
end if;
data_q <= mem(to_integer(pop_head_ptr));
end if;
end process ram_access;



-- Mike Treseler

I forgot to mention:
the SRAM is actually a ZBT synchronous pipelined SRAM, so the data needs
to be presented to the SRAM 2 cycles after the control in Write
transactions, and also is available 2 cycles after control in Read
transactions.

Jo

Mike Treseler wrote:
> A synchronous fifo is just an SRAM that uses
> a push or pop counter for write or read addresses.
> Here is the guts of a block-ram based design:
>
> begin
> if rising_edge(clk) then
> if we = '1' then
> mem(to_integer(push_tail_ptr)) <= data_i; -- raw address
> end if;
> data_q <= mem(to_integer(pop_head_ptr));
> end if;
> end process ram_access;
>
>
>
> -- Mike Treseler


--
Dr Joachim Schambach
The University of Texas at Austin
Department of Physics
1 University Station C1600
Austin, Texas 78712-0264, USA
Phone: (512) 471-1303; FAX: (814) 295-5111
e-mail:

Jo Schambach wrote:
> I forgot to mention:
> the SRAM is actually a ZBT synchronous pipelined SRAM, so the data needs
> to be presented to the SRAM 2 cycles after the control in Write
> transactions, and also is available 2 cycles after control in Read
> transactions.

Well,
write some code, run some sims
or find someone in your department who can.

-- Mike Treseler