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VHDL - Subtype of User-Defined Type?

 
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Old 12-06-2007, 03:06 AM   #1
Exclamation Subtype of User-Defined Type?


Hi,

I tried to declare a subtype of a user-defined type like this:

TYPE test IS (a, b , c, d, e);
SUBTYPE subtest IS test (a, c, e);

However, Quartus v7.2 give me an error:
"Type Conversion near text or symbol "test" must have one argument", which I don't understand even after reading Quartus' help.

Can someone please explain what the error means? Is it even possible to do such subtype declaration? If so, what's the correct format?

Thank you.


tonyfai
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