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VHDL - std_logic_vector or bit_vector?

 
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Old 12-05-2007, 11:38 PM   #1
Default std_logic_vector or bit_vector?


What's the difference between std_logic_vector and bit_vector? When to use
one or the other? I'm coding a multiplier array (2 operands of 8 bits), what
type should I use?

Discuss,

Xiao



Xin Xiao
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Old 12-06-2007, 12:19 AM   #2
Mike Treseler
 
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Default Re: std_logic_vector or bit_vector?
Xin Xiao wrote:
> What's the difference between std_logic_vector and bit_vector? When to
> use one or the other? I'm coding a multiplier array (2 operands of 8
> bits), what type should I use?


numeric_std.unsigned

> Discuss,


Google,

http://groups.google.com/groups/sear...std+bit+vector


Mike Treseler
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