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[baggio_bupt]

I use ise to design a ram on xilinx spardan3e.When I run Synthesize about the code below, the Synthesize runs a long time and does not stop. May someone can tell me the reason? thanks!


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity vgaram is
port( clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data_o : out std_logic_vector(0 to 7);
data_i : in std_logic;
rwenable : in std_logic
);
end vgaram;

architecture vgaram_arch of vgaram is

type ramtype is array(0 to 19) of std_logic_vector(0 to 7);
signal vedioram : ramtype :=
(
"00000000","00000000","00000000","00000000","0 0000 000","00000000","00000000","00000000","00000000", " 00000000",
"00000000","00000000","00000000","00000000","0 0000 000","00000000","00000000","00000000","00000000", " 00000000"

);


begin

process(clk)
begin
if clk'event and clk = '1' then
if rwenable = '0' then
vedioram(conv_integer(addr(12 downto 3)))(conv_integer(addr(2 downto 0))) <= data_i;
else
data_o <= vedioram(conv_integer(addr(12 downto 3)));
end if;
end if;
end process;
end vgaram_arch;