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VHDL - Whats the use of Code inside an Entity Declaration |
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#1 |
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I only realised today that I can put sequential statements inside an
entity, rather than an architecture. So, other than asserts or similar to check the viability of given generics, what useful code can but put in there? From making a test entity, I also noticed that an assert I had that checked a generic, was not processed until the first delta cycle in modelsim. I had some outputs from another process written to the console before the assert inside the entity failed. Tricky |
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#2 |
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Posts: n/a
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On Dec 3, 11:45 am, Tricky <Trickyh...@gmail.com> wrote:
> I only realised today that I can put sequential statements inside an > entity, rather than an architecture. > > So, other than asserts or similar to check the viability of given > generics, what useful code can but put in there? > > From making a test entity, I also noticed that an assert I had that > checked a generic, was not processed until the first delta cycle in > modelsim. I had some outputs from another process written to the > console before the assert inside the entity failed. I think you can put any code that does not update a signal or shared variable in the entity statement part. Concurrent statements, including concurrent assertion statements, are implied processes, and processes execute in indeterminate order within the same delta cycle. If you really want something to fail prior to simulation starting, it needs to cause an error in elaboration. Things like illegal object declarations (subtype outside of root type's range, etc.) constant initialization, port-signal bounds mismatches, etc. should do the trick. But then the error message may not be too useful. You might be able to declare a constant initialized with a function call, taking the generic(s) as argument(s), and inside that function have one or more assertion statements. Andy Andy |
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