plese problem std_logic_vector

I want to implement this:

entity Project1 is
Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
Input1 : in STD_LOGIC_VECTOR;
Input2: in STD_LOGIC_VECTOR;
Result: out STD_LOGIC_VECTOR);
end Project1;

I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How can
i do this?

Xiao Xin

Xin Xiao

Xin Xiao a écrit:
>
> I want to implement this:
>
> entity Project1 is
> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> Input1 : in STD_LOGIC_VECTOR;
> Input2: in STD_LOGIC_VECTOR;
> Result: out STD_LOGIC_VECTOR);
> end Project1;
>
> I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How can
> i do this?

You do that:

entity Project1 is
Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
Input1 : in STD_LOGIC;
Input2: in STD_LOGIC;
Result: out STD_LOGIC);
end Project1;


--
Vince

Vince

"Vince" <> wrote in message
news: ...
> Xin Xiao a écrit:
>>
>> I want to implement this:
>>
>> entity Project1 is
>> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
>> Input1 : in STD_LOGIC_VECTOR;
>> Input2: in STD_LOGIC_VECTOR;
>> Result: out STD_LOGIC_VECTOR);
>> end Project1;
>>
>> I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How
>> can
>> i do this?
>
> You do that:
>
> entity Project1 is
> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> Input1 : in STD_LOGIC;
> Input2: in STD_LOGIC;
> Result: out STD_LOGIC);
> end Project1;
>
>
> --
> Vince

or

Input1 : in STD_LOGIC_VECTOR(0 downto 0);

maybe?
HTH., Syms.

Symon

On Dec 2, 3:09 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> "Vince" <debo...@free.fr> wrote in message
>
> news: ...
>
>
>
> > Xin Xiao a écrit:
>
> >> I want to implement this:
>
> >> entity Project1 is
> >> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> >> Input1 : in STD_LOGIC_VECTOR;
> >> Input2: in STD_LOGIC_VECTOR;
> >> Result: out STD_LOGIC_VECTOR);
> >> end Project1;
>
> >> I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How
> >> can
> >> i do this?
>
> > You do that:
>
> > entity Project1 is
> > Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> > Input1 : in STD_LOGIC;
> > Input2: in STD_LOGIC;
> > Result: out STD_LOGIC);
> > end Project1;
>
> > --
> > Vince
>
> or
>
> Input1 : in STD_LOGIC_VECTOR(0 downto 0);
>
> maybe?
> HTH., Syms.

By "want no range" do you mean you want undeclared range? If so, that
works fine, but not for the top level entity. If you have
unconstrained ports, their range is defined in the instantiation. A
top level entity is not instantiated anywhere, so there is no
definition for the range.

Andy

Andy

Yes Andy, this is what I meant.

mmm, Ok so I declared this range in my entity,

Input1 : in STD_LOGIC_VECTOR (7 downto 0);

Then I do something like this:

add(Input1, Result);

and procedure "add" is

procedure add (v : in std_logic_vector; res: out integer) is

alias v1 : std_logic_vector (7 downto 0) is v;

Am I correct if I assume that I should get the vector "Input1" in "v1"
after calling the procedure "add"?

Xiao


"Andy" <> wrote in message
news:53b22204-86b2-445b-ad18-...
On Dec 2, 3:09 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> "Vince" <debo...@free.fr> wrote in message
>
> news: ...
>
>
>
> > Xin Xiao a écrit:
>
> >> I want to implement this:
>
> >> entity Project1 is
> >> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> >> Input1 : in STD_LOGIC_VECTOR;
> >> Input2: in STD_LOGIC_VECTOR;
> >> Result: out STD_LOGIC_VECTOR);
> >> end Project1;
>
> >> I got error in STD_LOGIC_VECTOR, but I want no range in this vector.
> >> How
> >> can
> >> i do this?
>
> > You do that:
>
> > entity Project1 is
> > Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> > Input1 : in STD_LOGIC;
> > Input2: in STD_LOGIC;
> > Result: out STD_LOGIC);
> > end Project1;
>
> > --
> > Vince
>
> or
>
> Input1 : in STD_LOGIC_VECTOR(0 downto 0);
>
> maybe?
> HTH., Syms.

By "want no range" do you mean you want undeclared range? If so, that
works fine, but not for the top level entity. If you have
unconstrained ports, their range is defined in the instantiation. A
top level entity is not instantiated anywhere, so there is no
definition for the range.

Andy

Xin Xiao

On Dec 3, 8:59 am, "Xin Xiao" <x...@x.com> wrote:
> Yes Andy, this is what I meant.
>
> mmm, Ok so I declared this range in my entity,
>
> Input1 : in STD_LOGIC_VECTOR (7 downto 0);
>
> Then I do something like this:
>
> add(Input1, Result);
>
> and procedure "add" is
>
> procedure add (v : in std_logic_vector; res: out integer) is
>
> alias v1 : std_logic_vector (7 downto 0) is v;
>
> Am I correct if I assume that I should get the vector "Input1" in "v1"
> after calling the procedure "add"?
>
> Xiao
>
> "Andy" <jonesa...@comcast.net> wrote in message
>
> news:53b22204-86b2-445b-ad18-...
> On Dec 2, 3:09 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>
>
>
> > "Vince" <debo...@free.fr> wrote in message
>
> >news: r...
>
> > > Xin Xiao a écrit:
>
> > >> I want to implement this:
>
> > >> entity Project1 is
> > >> Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> > >> Input1 : in STD_LOGIC_VECTOR;
> > >> Input2: in STD_LOGIC_VECTOR;
> > >> Result: out STD_LOGIC_VECTOR);
> > >> end Project1;
>
> > >> I got error in STD_LOGIC_VECTOR, but I want no range in this vector.
> > >> How
> > >> can
> > >> i do this?
>
> > > You do that:
>
> > > entity Project1 is
> > > Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
> > > Input1 : in STD_LOGIC;
> > > Input2: in STD_LOGIC;
> > > Result: out STD_LOGIC);
> > > end Project1;
>
> > > --
> > > Vince
>
> > or
>
> > Input1 : in STD_LOGIC_VECTOR(0 downto 0);
>
> > maybe?
> > HTH., Syms.
>
> By "want no range" do you mean you want undeclared range? If so, that
> works fine, but not for the top level entity. If you have
> unconstrained ports, their range is defined in the instantiation. A
> top level entity is not instantiated anywhere, so there is no
> definition for the range.
>
> Andy

Yes, you are correct. I assume your example procedure is just an
academic exercise? Otherwise, the code will not elaborate if Input1 is
anything but 8 bits long. You can get the range (or length, etc.) of
an unconstrained port by using the appropriate attribute of it. In
this case, v'length would be 8 inside this instantiation of add(). A
better alias declaration would be:

alias v1: std_logic_vector(v'length - 1 downto 0) is v;

Which would normalize the range of v1 to be the correct length, but
with downto direction, and ending at 0, no matter what the index range
of input1 was (i.e. input1 might have been slv(8 to 15). This is
always a good thing to do inside architectures or subprograms with
unconstrained ports, if your implementation relies on a specific index
ordering, etc. Most folks do it with a variable declaration,
initialized to the value of the port, but either way works, so long as
your tool supports it.

variable v1 : std_logic_vector(v'length - 1 downto 0) := v;

Andy

Andy