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VHDL - Quartus 2 - Code hangs while trying to elaborate entity

 
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Old 11-25-2007, 09:58 AM   #1
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Using the Quartus 2 software, when i attempt to compile the code seen below, the compiler hangs (tried waiting for up to 30 mins.) at 9% in the "Analysis & Synthesis" section. Is this a common error or does this mean my code is too elaborate (long loops) or any other suggestions that might cause this to happen.

This code is used to output 128 different sample codes at a certain time interval to a DAC in a parallel fashion. Basically, trying to create a sine wave with 128 samples. Using the clock count to create different frequencies for sound synthesis.

Any help is greatly appreciated!!!

Thanks so much in advance

entity wave is

port ( delay_countn : in integer;
clk : in std_logic;
dacout : out std_logic_vector (5 downto 0));

end wave;

architecture behavior of wave is

begin

process
variable dacout2, dacout3: std_logic_vector (5 downto 0);
variable u, sample : integer;

begin

wait until (clk'event and clk='1');

dacout2 := "100000";
dacout3 := "100001";
u := 0;
sample := 0;

if (delay_countn > 10) then

L : loop

k: loop

u := u + 1;

if (u = delay_countn and (sample < 32 or sample > 95)) then
dacout <= dacout2;
dacout2 := dacout2 + 1;
end if;

if (u = delay_countn and sample > 31 and sample < 96) then
dacout <= dacout2;
dacout2 := dacout2 - 1;
end if;

exit k when (u = delay_countn);

end loop;


sample := sample + 1;
if (sample < 32 or sample > 95) then
dacout3 := dacout3 + 1;
else dacout3 := dacout3 - 1;
end if;
exit L when sample = 128;

end loop;
end if;
end process;
end behavior;


prophecy8445
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