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want to write assertions in a seperate VHDL file

 
 
anupam
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      02-15-2006


hi,
I want to use assertions (PSL or may be OVL) for the verification of my
VHDL design but the problem is ,i don't know where to write assertions
.....
I can't disturb the RTL and moreover the VHDL doesn't have a "file
include " option in it so the only place i can write asserton, is the
testbench ,but its better to write them in a seperate file..

Is there a way in VHDL so that i can write my assertions in a seperate
file and and use them during simulations ( like a package or anything
of that kind ....)

regards,
Anupam Jain

 
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Ajeetha
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      02-15-2006
Anupam,
It is possible with PSL and/or SVA. PSL has this "vunit" that
can be used for this. SVA has a even more flexible "bind" for similar
purpose. OVL - tough to do, though one may be able to use XMR via
SignalSpy/hdl_xmr etc.

HTH
Ajeetha, CVC

 
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Hans
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      02-15-2006
Hi Anupam

"anupam" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
>
>
> hi,
> I want to use assertions (PSL or may be OVL) for the verification of my


Go for PSL, not that difficult to learn and much much more powerful and
flexible than OVL but then again OVL is free and PSL cost an arm and a leg.

> VHDL design but the problem is ,i don't know where to write assertions
> ....


you can either embed PSL in your VHDL comments, example:

-- psl default clock is rising_edge(clk);
-- psl property mutex is never (rd and wr);

Or put them all in a separate vunit file and link that file to your
architecture.
vunit bla_unit(bla_entity_name (bla_architecure_name)){
default clock is rising_edge(clk);
property mutex is never (rd and wr);
assert mutex;
}

> I can't disturb the RTL and moreover the VHDL doesn't have a "file
> include " option in it so the only place i can write asserton, is the
> testbench ,but its better to write them in a seperate file..


In that case you have to go for a vunit. If you have access to Modelsim than
you can also use Signalspy within your vunit which is very handy!

Hans

www.ht-lab.com


>
> Is there a way in VHDL so that i can write my assertions in a seperate
> file and and use them during simulations ( like a package or anything
> of that kind ....)
>
> regards,
> Anupam Jain
>



 
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