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VHDL - Accessing signals through strings |
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11-20-2007, 11:45 AM
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#1 |
Accessing signals through strings
Hello,
Does anyone know how to access a signals' value by referencing that signal name though a string? e.g. I am reading in my signal names from a file. I then wish to print back out to a file the corresponding signal values. Hope that is clear. Regards John john.williamson@aculab.com |
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11-20-2007, 12:29 PM
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#2 |
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Posts: n/a
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Re: Accessing signals through strings
On Tue, 20 Nov 2007 03:45:34 -0800 (PST),
wrote: >Does anyone know how to access a signals' value by referencing that >signal name though a string? Not in VHDL, unless you write a very frightening "case" statement. If you are using ModelSim, you should check out the "SignalSpy" tool. Otherwise, it's something that you could do through the simulator's C-language interface. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. Jonathan Bromley |
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11-20-2007, 01:09 PM
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#3 |
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Re: Accessing signals through strings
> Not in VHDL, unless you write a very frightening "case"
> statement. > Thanks for the prompt reply Jonathan. Regards John john.williamson@aculab.com |
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