Simple VHDL/ModelSim Problem

I am using: xilinx 9.2.03i
modelsim xe III 6.2g

My code is for an 8-bit shift adder. When I program my FPGA everything works correctly, now my problem is that I can't get the timing diagram in modelsim to reflect what is happening in real life. I have made the testbench in the xilinx project navigator and then hit "Simulate Behavioral Model".

I've been scouring the internet for an answer but have yet to find anything, any help would be GREATLY appreciated.

Also, sorry for using a bugmenot account I registered earlier today and still haven't recieved a confirmation email.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Project is
	port(	Clk	:	in	std_logic;
		datain	:	in	std_logic;
		dataout	:	out	std_logic_vector(7 downto 0) := "00000000";
		SSG	:	out	std_logic_vector(0 to 7);
		En	:	out	std_logic_vector(3 downto 0));
end Project;

architecture Behavioral of Project is
	signal x : std_logic;
	signal data : std_logic_vector(7 downto 0) := "00000000";
	signal tempclk : std_logic_vector(27 downto 0) := "0000000000000000000000000000";
begin
	
	En <= "0111";
	
	process(Clk)
		begin
			if Clk='1' and Clk'event then
			tempclk <= tempclk + "0000000000000000000000000001";
			end if;
		end process;
	
	x <= tempclk(26);
	
	process(x)
		begin
			if x='1' and x'event then
			dataout(0) <= datain;
			dataout(1) <= data(0);
			dataout(2) <= data(1);
			dataout(3) <= data(2);
			dataout(4) <= data(3);
			dataout(5) <= data(4);
			dataout(6) <= data(5);
			dataout(7) <= data(6);
			data(7) <= data(6);
			data(6) <= data(5);
			data(5) <= data(4);
			data(4) <= data(3);
			data(3) <= data(2);
			data(2) <= data(1);
			data(1) <= data(0);
			data(0) <= datain;
			end if;
	
			case x is
				when '0' => SSG <= "00000010";
				when others => SSG <= "10011110";
			end case;
		end process;
	
end Behavioral;

bugmenotnot

[bugmenotnot]

I figured out what the problem was. If I don't use a tempclk then it works, otherwise I have to wait a LONG time for anything to happen.

bugmenotnot