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Simple question, reset a counter

Posts: n/a

I've created a FSM and, inside it, a counter to count the clock cycles
between transitions.

Maybe it's too simple but I don't see how can I reset the *counter* from
inside the state machine?


entity FSM is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;

end FSM;

architecture Behavioral of FSM is

component Counter
port ( Clk : in STD_LOGIC;
Clear : in STD_LOGIC;
end component;


U1: Counter port map (<I don't know what signals include here>);


when S2 =>
if .... then
Next_State <= S3;
Signal <= '1'; -- Reset the counter
end if;


The "Reset" signal of the FSM returns to state S0, so that's not what I
want, I only want to reset the counter.

I'm stuck, any ideas?

Reply With Quote
Jonathan Bromley
Posts: n/a
On Mon, 19 Nov 2007 19:33:02 +0100, Dan wrote:

>I've created a FSM and, inside it, a counter to count the clock cycles
>between transitions.
>Maybe it's too simple but I don't see how can I reset the *counter* from
>inside the state machine?

You've already done it! Create a signal that's an output from
the FSM - as you've done, in your transition from state S2 to S3.
Use that signal directly as the counter's reset.

Even better, don't instantiate a counter at all. Instead,
provide a variable in your FSM process that counts down on
every clock. Some states (the states that need the counter)
will wait until the counter hits zero before proceeding.
Transitions into those states will preset the counter
to an appropriate timeout value. This has been discussed
many times here, including at least one very recent occasion.
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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