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VHDL - beginner: 3:8 decoder with enable

 
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Old 11-19-2007, 05:46 PM   #1
Default beginner: 3:8 decoder with enable


i want to write the architecture of 3:8 decoder with enable ...

anyone can help ,

i wrote the entity
Code:
ENTITY Decoder3_8_Enable IS port (a: in std_logic_vector(2 downto 0); e: in std_logic ; y:out std_logic_vector(7 downto 0)); END ENTITY Decoder3_8_Enable;


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