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VHDL language is out of date! Why? I will explain.

 
 
Helmut
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      11-23-2007
I agree that VHDL has some disadvantages when I comes to syntax
features.But if there is not a synthesis tools, I just canīt use any
other language to program my FPGA.
 
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Mike Treseler
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      11-23-2007
Helmut wrote:
> I agree that VHDL has some disadvantages when I comes to syntax
> features.But if there is not a synthesis tools, I just canīt use any
> other language to program my FPGA.


Sorry. Let me fix that subject line.
I agree with you.
The thread went off on a tangent
as they often do

-- Mike Treseler


 
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Nico Coesel
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      11-23-2007
Paul Taylor <(E-Mail Removed)> wrote:

>On Sat, 17 Nov 2007 20:52:59 +0100, Jan Decaluwe wrote:
>
>> The synthesizable RTL subset is what it is. Conceptually, there's little
>> to be gained from using MyHDL or whatever instead of VHDL for this.

>
>I think that there is something to be gained from using 'whatever', but it
>depends - if you are full-time vhdler working on small or large FPGA
>designs then fine; if you are an electronics engineer who on a reasonably
>regular basis has an FPGA that needs to be designed/verified then vhdl is
>(IMO of course) too complex, and, for test benches in particular, too
>cumbersome.


In that perpective, using C would have made much more sense. Most
electronics engineers can write software in C. Having to use python is
like trading one obscure language for another.

Anyway, I've been using VHDL for a couple of years now (on and off)
and I must say it has its disadvantages, but it also is pretty
powerfull. I particulary like the functions and records. They allow me
to write complex stuff in just a few lines.

--
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Paul Taylor
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      11-24-2007
On Thu, 22 Nov 2007 13:33:14 -0800, Mike Treseler wrote:

> Paul Taylor wrote:
>> ...
>> I also have a marked keyword, which is a safeguard
>> because sometimes I stupidly use the wrong variable, e.g. an
>> unsynchronised signal instead of one that I have synchronised for use
>> (especially when I come back to change some code).

>
> Interesting.
> I now handle this manually by using annoying
> identifiers for the unsynch nodes.
> Maybe "run_glitchy" vs "run".
>
>> I would be interested to know what mistakes others commonly make, that are
>> found by the VHDL compiler.

>
> OK here's mine.
> I get automated mistake-finding at the
> editor, analysis, and elaboration level
> of each library unit.
>
> 1. Emacs vhdl-mode completes keywords
> and identifiers, matches most parens
> and prompts for clauses in a keyword statement.
> This prevents most syntax errors from happening.
>
> 2. I run simulation analysis
> vcom -c mydesign.vhd
> from an editor function key every few lines of code.
> This step finds the most errors
> but puts the cursor right on each one
> and tells me what's wrong.
>
> I would estimate:
> 90% syntax punctuation: missing or excess : ; ) etc.
> 10% static mismatch of code with local or library subtypes.
> Length, range etc.
> 10% signature mismatch of code and local or library subprograms
>
> At the top level, Emacs vhdl-make automatically finds
> units with multiple declarations in the project path, like this:
> WARNING: Architecture declared twice (used 1.): "synth" of "cnt_decode"
> 1. in "~/vhdl/play/cnt__decode.vhd" (line 1
> 2. in "~/vhdl/play/cnt_decode.vhd" (line 1
>
> 3. elaboration:
> vsim -c mydesign
> will find most runtime mismatches
> and give a pretty good description of what's wrong.
> Some messages are more cryptic hints at infinite loops,like
> ** Fatal: Write failure in vlm process (32,-1)
>
> That leaves the functional errors to simulation
> viewers and assertions, but I have no automated
> method for this.
>
> -- Mike Treseler


Thanks for info,

Paul.
 
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reiner@hartenstein.de
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      11-24-2007

See the extremely bad opinion of Joe Costello as former CEO of
CADENCE:
http://xputers.informatik.uni-kl.de/....html#Costello

Archimedes Neutrino


http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> Just look at its syntax. It is so archaic that anyone who had any deal
> with Python will just laugh. Try, say, to create a simple VGA
> controller, which is simply readable.
>
> VHDL's Ada syntax is also very error prone. Instead of having all this
> archaic constructions and surplus operators, it would be much more
> productive just to start thinking about to create another hi-level HDL
> that has absolutely another conceptual design and simple syntax.
>
> Any good language should be so simple as possible and any program in
> this language should be short and clear. Such language should support
> associative arrays, that should help designing large FSMs; should
> support simple mechanism of type conversions and so on...
>
> Conceptually VHDL is not bad at all, it supports a lot of things, well
> in theory. But in praxis ...
>
> And don't forget about future FPGAs, about future SoCs, which will
> have integrated MEMS arrays, and other stuff. Try to understand how
> much complexer they are to be designed in so unproductive way using so
> primitive languages.

 
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Jan Decaluwe
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      11-25-2007
Wolfgang Grafen wrote:

> MyHDL is a one man show.


MyHDL is set up as a typical open-source project. It is as open as possible
and encourages people to contribute. People do contribute when it's useful
to them, and they do so for MyHDL. Of course, there is a benevolent dictator
(yours truly) to set the pace and to arbitrate.

So the statement above is disrespectful to all those who contributed in some
form to MyHDL. I immediately add that I'll take the blame: I haven't
acknowledged these contributions explicitly enough in the past. I'll try
to fix that, and I apologize to all those concerned.

> I doubt that Python is the ideal language based for
> hardware description. I believe it is possible to design a very concise dynamic
> language for hardware design. But this will significantly more than one person
> to bring it up. My impression is MyHDL is not very suitable for large projects now.


doubt, believe, impression ... instead of spreading FUD, why not just
tell us about our complaints and the features you are missing. (Not in this
newsgroup of course.)

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
 
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Nico Coesel
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      11-25-2007
Jan Decaluwe <(E-Mail Removed)> wrote:

>Wolfgang Grafen wrote:
>
> > I doubt that Python is the ideal language based for
>> hardware description. I believe it is possible to design a very concise dynamic
>> language for hardware design. But this will significantly more than one person
>> to bring it up. My impression is MyHDL is not very suitable for large projects now.

>
>doubt, believe, impression ... instead of spreading FUD, why not just
>tell us about our complaints and the features you are missing. (Not in this
>newsgroup of course.)


Aside the obstacles I mentioned in my earlier post, I'm also concerned
about the ability of MyHDL to write clever code. I would like to know
how you can implement a 16 to 4 priority encoder in MyHDL....

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Jan Decaluwe
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      11-26-2007
Nico Coesel wrote:

> Aside the obstacles I mentioned in my earlier post, I'm also concerned
> about the ability of MyHDL to write clever code. I would like to know
> how you can implement a 16 to 4 priority encoder in MyHDL....


Just like you would in VHDL or Verilog: loop over the input bits
and break out early as soon as a '1' is found.

No cleverness needed, just an HDL with support for procedural statements.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
 
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bedrr bedrr is offline
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      11-26-2007
so think about verilog !
 
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Wolfgang Grafen
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      11-26-2007
Jan Decaluwe schrieb:
> Wolfgang Grafen wrote:
>
>> MyHDL is a one man show.

>
> MyHDL is set up as a typical open-source project. It is as open as possible
> and encourages people to contribute. People do contribute when it's useful
> to them, and they do so for MyHDL. Of course, there is a benevolent
> dictator
> (yours truly) to set the pace and to arbitrate.
>
> So the statement above is disrespectful to all those who contributed in
> some
> form to MyHDL. I immediately add that I'll take the blame: I haven't
> acknowledged these contributions explicitly enough in the past. I'll try
> to fix that, and I apologize to all those concerned

Whether it is disrespectful or not depends on the view point. For one
person or probably a hand full person it is a great effort. I didn't
mean it in a negative way.

>
> > I doubt that Python is the ideal language based for
>> hardware description. I believe it is possible to design a very
>> concise dynamic
>> language for hardware design. But this will significantly more than
>> one person
>> to bring it up. My impression is MyHDL is not very suitable for large
>> projects now.

>
> doubt, believe, impression ... instead of spreading FUD, why not just
> tell us about our complaints and the features you are missing. (Not in this
> newsgroup of course.)
>

First of all, I miss sufficient documentation and really useful examples. A
large project I think of has some millions gate coded in hundreds of blocks
designed by five or more hardware designers with several clock domains
and will finally work. It should be able to efficiently simulate, write
back synthesis timing information and so on.

I like Python for a long time. Python was not designed for hardware
design. The ideal language has the most comprehensive syntax and good
support e.g. for parallel processes. It can be done in Python, but with
less comprehensive syntax and less simulation performance compared to an
optimised language.

Of course, this is only my opinion. I promise I will look over MyHDL
again (did it last half a year ago).

Best regards

Wolfgang
 
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