Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > clock-domain-crossing simulation in Altera

Reply
Thread Tools

clock-domain-crossing simulation in Altera

 
 
kpram kpram is offline
Junior Member
Join Date: Nov 2007
Posts: 1
 
      11-15-2007
Hi all

Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".

In Xilinx this is done by applying the ASYNC_REG attribute. But haven't found anything similar in Altera.

regards,

Kostas
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Timing Simulation with Altera-Modelsim faust861 VHDL 0 06-23-2010 09:25 AM
Stopping the simulation in Modelsim Altera Starter Edition/Linux? Petter Gustad VHDL 1 09-19-2009 01:46 PM
Problem with post-route simulation / timing simulation jasperng VHDL 0 11-27-2008 06:23 AM
equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera StratixII GX-90 chaitu VHDL 1 01-28-2008 12:46 PM
Functional VHDL Simulation Problem with Altera dual clock fifo Thomas Fischer VHDL 2 04-11-2005 01:29 PM



Advertisments