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Modelsim-altera crash, need help.

 
 
Bigyellow
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Posts: n/a
 
      11-14-2007
Hello,

My Modelsim(Altera edition) crashed when I tried to simulate my own
NIOS II system.
The modelsim version is 6.1g and launched from NIOS II IDE 7.1.

The error message are

# ** Error: (vsim-3) System call VirtualAlloc() failed.
# The parameter is incorrect.
#
# . (GetLastError() = 87)
# ** Fatal: (vsim-4) ****** Memory allocation failure. *****
# Please check your system for available memory and swap space.
# ** Fatal: (vsim-4) ****** Memory allocation failure. *****
# Please check your system for available memory and swap space.

-rgs
Jim

 
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HT-Lab
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Posts: n/a
 
      11-14-2007

"Bigyellow" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Hello,
>
> My Modelsim(Altera edition) crashed when I tried to simulate my own
> NIOS II system.
> The modelsim version is 6.1g and launched from NIOS II IDE 7.1.
>
> The error message are
>
> # ** Error: (vsim-3) System call VirtualAlloc() failed.
> # The parameter is incorrect.
> #
> # . (GetLastError() = 87)
> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
> # Please check your system for available memory and swap space.
> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
> # Please check your system for available memory and swap space.


Are you trying to simulate a large memory? If so look in the user manual
under VHDL simulation on how to simulate memory using shared variables.

Hans.
www.ht-lab.com

>
> -rgs
> Jim
>



 
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Paul Uiterlinden
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Posts: n/a
 
      11-14-2007
HT-Lab wrote:

>
> "Bigyellow" <(E-Mail Removed)> wrote in message
> news:(E-Mail Removed) ups.com...
>> Hello,
>>
>> My Modelsim(Altera edition) crashed when I tried to simulate my own
>> NIOS II system.
>> The modelsim version is 6.1g and launched from NIOS II IDE 7.1.
>>
>> The error message are
>>
>> # ** Error: (vsim-3) System call VirtualAlloc() failed.
>> # The parameter is incorrect.
>> #
>> # . (GetLastError() = 87)
>> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
>> # Please check your system for available memory and swap space.
>> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
>> # Please check your system for available memory and swap space.

>
> Are you trying to simulate a large memory? If so look in the user manual
> under VHDL simulation on how to simulate memory using shared variables.


IMHO, using a shared variable for that purpose is utter nonsense. It better
can be done using a normal variable and a single process. It avoids the
problem of possibly introducing non-deterministic results through race
conditions. That is: if the two processes should run at exact the same
delta, which of the two processes will actually be first?

With a single process, it is _you_ who decides what should happen in the
case of for example a concurrent read and write access.

But of course you are right: memory should be modeled using a variable, not
a signal.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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hans64@ht-lab.com
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Posts: n/a
 
      11-15-2007
On Nov 14, 9:11 pm, Paul Uiterlinden <(E-Mail Removed)> wrote:
> HT-Lab wrote:
>
> > "Bigyellow" <(E-Mail Removed)> wrote in message
> >news:(E-Mail Removed) oups.com...
> >> Hello,

>
> >> My Modelsim(Altera edition) crashed when I tried to simulate my own
> >> NIOS II system.
> >> The modelsim version is 6.1g and launched from NIOS II IDE 7.1.

>
> >> The error message are

>
> >> # ** Error: (vsim-3) System call VirtualAlloc() failed.
> >> # The parameter is incorrect.
> >> #
> >> # . (GetLastError() = 87)
> >> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
> >> # Please check your system for available memory and swap space.
> >> # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
> >> # Please check your system for available memory and swap space.

>
> > Are you trying to simulate a large memory? If so look in the user manual
> > under VHDL simulation on how to simulate memory using shared variables.

>
> IMHO, using a shared variable for that purpose is utter nonsense.


Who are we to argue with Modelsim

> can be done using a normal variable and a single process. It avoids the
> problem of possibly introducing non-deterministic results through race
> conditions. That is: if the two processes should run at exact the same
> delta, which of the two processes will actually be first?


If you look at the model (assuming you have access to Modelsim) you
will see they also use a single process for reading and writing. The
second process is for init purposes,

Hans
www.ht-lab.com

>
> With a single process, it is _you_ who decides what should happen in the
> case of for example a concurrent read and write access.
>
> But of course you are right: memory should be modeled using a variable, not
> a signal.
>
> --
> Paul Uiterlindenwww.aimvalley.nl
> e-mail addres: remove the not.


 
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Paul Uiterlinden
Guest
Posts: n/a
 
      11-15-2007
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:


>>
>> IMHO, using a shared variable for that purpose is utter nonsense.

>
> Who are we to argue with Modelsim


I don't see the problem.
In fact, I should report this as a service request.

>> can be done using a normal variable and a single process. It avoids the
>> problem of possibly introducing non-deterministic results through race
>> conditions. That is: if the two processes should run at exact the same
>> delta, which of the two processes will actually be first?

>
> If you look at the model (assuming you have access to Modelsim) you
> will see they also use a single process for reading and writing. The
> second process is for init purposes,


All the more stupid. It can all be combined into one process.

Original code (with as extra bonus: unused variable declared in process
initialize):

ARCHITECTURE style_93 OF memory IS
----------------------------------------------------------------------
SHARED VARIABLE ram : ram_type;
----------------------------------------------------------------------
BEGIN
memory: PROCESS (cs) IS
VARIABLE address : natural;
BEGIN
IF rising_edge(cs) THEN
address := sulv_to_natural(add_in);
IF (mwrite = '1') THEN
ram(address) := data_in;
END IF;
data_out <= ram(address);
END IF;
END PROCESS memory;

-- illustrates a second process using the shared variable
initialize: PROCESS (do_init) IS
VARIABLE address : natural;
BEGIN
IF rising_edge(do_init) THEN
FOR address IN 0 TO nwords-1 LOOP
ram(address) := data_in;
END LOOP;
END IF;
END PROCESS initialize;
END ARCHITECTURE style_93;


Single process:

ARCHITECTURE style_93 OF memory IS
BEGIN
memory: PROCESS (cs, do_init) IS
VARIABLE ram : ram_type;
VARIABLE address : natural;
BEGIN
IF rising_edge(do_init) THEN
FOR a IN 0 TO nwords-1 LOOP
ram(a) := data_in;
END LOOP;
END IF;

IF rising_edge(cs) THEN
address := sulv_to_natural(add_in);
IF mwrite = '1' THEN
ram(address) := data_in;
END IF;
data_out <= ram(address);
END IF;
END PROCESS memory;
END ARCHITECTURE style_93;


--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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