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Error "Unsupported Clock Statement" when asigning a value to a signal

 
 
kushal kushal is offline
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Join Date: Jul 2012
Posts: 4
 
      07-05-2012
hi ... in the specified line, iam getting unsupported clock statement error while synthesizing the code.. simulation worked well but this error is shown during synthesis. plz help as im not able to figure out why ..

process(b_clkx
begin
if((rising_edge(b_clkx) and (state = idle) and (rxd_data = '0') ) then
state <= start_detected;
elsif((rising_edge(b_clkx) and (state = start_detected)
and (rxd_data = '0') and (ct1 = 3)) then
state <= recv_data; ----------------------------------------------
elsif(((rising_edge(b_clkx) and (rxd_data = '1')
and (ct1=0) and (ct2=0)) or((state = recv_data)
and (ct1 = 7) and (ct2 = 9))) then
state <= idle;
end if;
end process;
 
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JohnDuq JohnDuq is offline
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Join Date: Dec 2008
Posts: 88
 
      07-09-2012
What logic family are you synthesizing for? You might try simplifying your clock statement first. Change:

if((rising_edge(b_clkx) and (state = idle) and (rxd_data = '0') ) then

to

if((rising_edge(b_clkx)) then
if((state = idle) and (rxd_data = '0') ) then


Also, it shouldn't matter for synthesis, but I'm surprised you got away with it for simulation; your process line should read:

process( b_clkx, state, rxd_data, start_detected, ct1, recv_data, ct2, idle)
 

Last edited by JohnDuq; 07-09-2012 at 12:55 PM..
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kushal kushal is offline
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Join Date: Jul 2012
Posts: 4
 
      07-12-2012
hi
thnx for replying to my post. I want d code to be synthesizible for spartan 6 or spartan 3A. I changed d code as per your suggestion and the error isnt der anymore. Also after synthesis, i got some warnings. so is it ok to proceed or i shd try to remove dose warnings as well ?? Im new to VHDL so not sure which statements are synthesizible and which are not. plz help me which sites or texts should i go thru to be perfect in synthesizing d code rather dan only simulating. der seems to be many differences in code for sim and synth. i exatly donno which codes are synthesizible and which are not.
 

Last edited by kushal; 07-12-2012 at 03:40 PM..
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JohnDuq JohnDuq is offline
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      07-12-2012
A lot of subtleties like this are device specific, so you have to see where the issues arise and figure out another way to do what you want. Warnings mean something isn't optimum; it is up to you to decide if it is worth perfecting; what are the consequences of leaving it as-is?

This is a great site for posting questions; there are a lot of users who are much better experts than I am. For device specific questions like this clocking issue, I'd try the Xilinx forum (http://forums.xilinx.com/t5/Silicon-...s/ct-p/SILICON). I've only posted CPLD questions there but that group is very knowledgeable.

Happy coding!
 
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kushal kushal is offline
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Join Date: Jul 2012
Posts: 4
 
      07-12-2012
thnx for d forum .. hope i can gain some knowledge thru that forum .. one more thing, you said d process line should read:

process( b_clkx, state, rxd_data, start_detected, ct1, recv_data, ct2, idle)

instead of

process(b_clkx)

but i thought as i was monitoring the d other signals for all b_clkx edges i thought d sensitivity list is sufficient with b_clkx. Is it right dis way or der is some more reasoning attaced to create sensitivity list. please help me out in this matter..
 
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JohnDuq JohnDuq is offline
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      07-12-2012
If those are local (combinatorial) variables you need them in the process line. If they are synchronized to the d clock then you might be okay.

As I understand it, the process block will only be processed when one of the variables (signals) in the process parameter list changes. If a variable changes and is not in the list it will be ignored until a variable in the list changes.
 
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