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please help 8 bit comparator

 
 
seice.kao@gmail.com
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      11-09-2007
library IEEE;
use IEEE.std_logic_1164.all;

entity SOP_Logic is
port(A : in std_logic_vector(7 down to 0);
B : in std_logic_vector(7 down to 0);
A_gt_B : in std_logic_vector(7 down to 0);
B_gt_A : in std_logic_vector(7 down to 0);
OUT7: out std_logic_vector(7 down to 0)
);

end entity SOP_Logic;

architechcture STRUCTURAL of SOP_Logic is


component NAND_gate2 is
port(X,Y,:in bit; Qut bit);
end component NAND_gate2;

component NAND_gate3 is
port(X,Y,Z:in bit; Qut bit);
end component NAND_gate3;


signal OUT1, OUT2, OUT3, OUT4:bit;

begin

G1: NAND_gate3 port map (X => not A,Y=>B,Z=>not A_gt_B, Q=> OUT3);
G2 : NAND_gate3 port map (X=> not B_gt_A, Y=>A, Z=>not B,Q=>OUT4);
G3: NAND_gate2 port map (X=> OUT3, Y=> not B_gt_A, Q=>OUT1);
G4: NAND_gate2 port map (X=>OUT4, Y=> not A_gt_B, Q=>OUT2);
G5: NAND_gate2 port map (X=>OUT1, Y=>OUT2, Q=>OUT7);

end STRUCTURAL;

 
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Andy
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      11-12-2007
On Nov 9, 1:39 pm, (E-Mail Removed) wrote:
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity SOP_Logic is
> port(A : in std_logic_vector(7 down to 0);
> B : in std_logic_vector(7 down to 0);
> A_gt_B : in std_logic_vector(7 down to 0);
> B_gt_A : in std_logic_vector(7 down to 0);
> OUT7: out std_logic_vector(7 down to 0)
> );
>
> end entity SOP_Logic;
>
> architechcture STRUCTURAL of SOP_Logic is
>
> component NAND_gate2 is
> port(X,Y,:in bit; Qut bit);
> end component NAND_gate2;
>
> component NAND_gate3 is
> port(X,Y,Z:in bit; Qut bit);
> end component NAND_gate3;
>
> signal OUT1, OUT2, OUT3, OUT4:bit;
>
> begin
>
> G1: NAND_gate3 port map (X => not A,Y=>B,Z=>not A_gt_B, Q=> OUT3);
> G2 : NAND_gate3 port map (X=> not B_gt_A, Y=>A, Z=>not B,Q=>OUT4);
> G3: NAND_gate2 port map (X=> OUT3, Y=> not B_gt_A, Q=>OUT1);
> G4: NAND_gate2 port map (X=>OUT4, Y=> not A_gt_B, Q=>OUT2);
> G5: NAND_gate2 port map (X=>OUT1, Y=>OUT2, Q=>OUT7);
>
> end STRUCTURAL;


Can't use "not" operator in a port association list. The actual must
be a signal or a conversion function with one signal argument.

You could use a "conversion function" written around "not", but
conversion functions are not generally synthesizable.

Andy

 
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HT-Lab
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Posts: n/a
 
      11-12-2007

"Andy" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> On Nov 9, 1:39 pm, (E-Mail Removed) wrote:

...snip
>
> Can't use "not" operator in a port association list. The actual must
> be a signal or a conversion function with one signal argument.


Come on Mentor/Aldec/Synopsys/Cadence/SymphonyEDA/GHDL/GreenMoutain/.. start
supporting VHDL2006!!

Hans
www.ht-lab.com



> You could use a "conversion function" written around "not", but
> conversion functions are not generally synthesizable.
>
> Andy
>



 
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Paul Uiterlinden
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      11-12-2007
Andy wrote:

> Can't use "not" operator in a port association list. The actual must
> be a signal or a conversion function with one signal argument.
>
> You could use a "conversion function" written around "not",


No need for that. Even without VHDL-2006, as Hans suggested.

The not operator is also a function. You need to surround the name with
double quotes. Since the "not" function only takes one argument, it is a
valid conversion function. Hence you can write in a port map (input in this
case):

X => "not"(A),

> but conversion functions are not generally synthesizable.


No experience with that. With synthesizers, that is.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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backhus
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      11-13-2007
Hi Seice,
so what exactly is your homwork or lab assignment?
Building a magnitude comparator from nand gates (and only nand gates)?

In that case using the not operator may not be allowed.
Instead you need to build an inverter with a nand gate.
Remember your digital basics lecture:

A nand A = not A

So you need some more signals and nand2 instances.

But if your assignment is just to write a nice magnitude comparator:

something like

if (A > B) then
A_gt_B <= '1';
end if;

etc...will be much shorter and easier to read than your code.

Have a nice simulation

Eilert




http://www.velocityreviews.com/forums/(E-Mail Removed) schrieb:
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity SOP_Logic is
> port(A : in std_logic_vector(7 down to 0);
> B : in std_logic_vector(7 down to 0);
> A_gt_B : in std_logic_vector(7 down to 0);
> B_gt_A : in std_logic_vector(7 down to 0);
> OUT7: out std_logic_vector(7 down to 0)
> );
>
> end entity SOP_Logic;
>
> architechcture STRUCTURAL of SOP_Logic is
>
>
> component NAND_gate2 is
> port(X,Y,:in bit; Qut bit);
> end component NAND_gate2;
>
> component NAND_gate3 is
> port(X,Y,Z:in bit; Qut bit);
> end component NAND_gate3;
>
>
> signal OUT1, OUT2, OUT3, OUT4:bit;
>
> begin
>
> G1: NAND_gate3 port map (X => not A,Y=>B,Z=>not A_gt_B, Q=> OUT3);
> G2 : NAND_gate3 port map (X=> not B_gt_A, Y=>A, Z=>not B,Q=>OUT4);
> G3: NAND_gate2 port map (X=> OUT3, Y=> not B_gt_A, Q=>OUT1);
> G4: NAND_gate2 port map (X=>OUT4, Y=> not A_gt_B, Q=>OUT2);
> G5: NAND_gate2 port map (X=>OUT1, Y=>OUT2, Q=>OUT7);
>
> end STRUCTURAL;
>

 
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Andy
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      11-13-2007
On Nov 12, 4:13 pm, Paul Uiterlinden <(E-Mail Removed)> wrote:
> Andy wrote:
> > Can't use "not" operator in a port association list. The actual must
> > be a signal or a conversion function with one signal argument.

>
> > You could use a "conversion function" written around "not",

>
> No need for that. Even without VHDL-2006, as Hans suggested.
>
> The not operator is also a function. You need to surround the name with
> double quotes. Since the "not" function only takes one argument, it is a
> valid conversion function. Hence you can write in a port map (input in this
> case):
>
> X => "not"(A),
>
> > but conversion functions are not generally synthesizable.

>
> No experience with that. With synthesizers, that is.
>
> --
> Paul Uiterlindenwww.aimvalley.nl
> e-mail addres: remove the not.


Paul,

Thanks for the trick, I forgot about that. There is one caveat,
though. If the port is of an unconstrained type, the conversion
function must return a constrained type result, so that the the true
width of the port can be determined statically. That is not a problem
in this application though.

I saw a paper several years ago about using conversion functions in
configuration port maps to accommodate inserting integer and vector
based models per configuration. They had to write a package of integer-
vector conversions of fixed widths. For those that have never tried
it, integer based models (even synthesizable ones) are MUCH faster
simulating than vector based models.

Andy

 
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Andy
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      11-13-2007
On Nov 13, 1:12 am, backhus <(E-Mail Removed)> wrote:
> Hi Seice,
> so what exactly is your homwork or lab assignment?
> Building a magnitude comparator from nand gates (and only nand gates)?
>
> In that case using the not operator may not be allowed.
> Instead you need to build an inverter with a nand gate.
> Remember your digital basics lecture:
>
> A nand A = not A
>
> So you need some more signals and nand2 instances.
>
> But if your assignment is just to write a nice magnitude comparator:
>
> something like
>
> if (A > B) then
> A_gt_B <= '1';
> end if;
>
> etc...will be much shorter and easier to read than your code.
>
> Have a nice simulation
>
> Eilert
>



Or even shorter:

A_gt_B <= '1' when A > B else '0';

But something tells me this was a homework assignment for structural
code.

Andy

 
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Paul Uiterlinden
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Posts: n/a
 
      11-13-2007
Andy wrote:

>> The not operator is also a function. You need to surround the name with
>> double quotes. Since the "not" function only takes one argument, it is a
>> valid conversion function. Hence you can write in a port map (input in
>> this case):
>>
>> X => "not"(A),

>
> Thanks for the trick, I forgot about that. There is one caveat,
> though. If the port is of an unconstrained type, the conversion
> function must return a constrained type result, so that the the true
> width of the port can be determined statically.


Ah yes, that's a nice one.

> That is not a problem in this application though.


Indeed. Most of the times I use this for those one bit signals that must be
inverted.

> I saw a paper several years ago about using conversion functions in
> configuration port maps to accommodate inserting integer and vector
> based models per configuration. They had to write a package of integer-
> vector conversions of fixed widths. For those that have never tried
> it, integer based models (even synthesizable ones) are MUCH faster
> simulating than vector based models.


I'm curious what you mean with integer based models. Does that include all
data, even if this data must be used in logic functions (such as and, or,
bit selection, etc)?

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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