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connecting std_logic inout ports and std_logic_vector inout port

 
 
=?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=
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      11-06-2007
Hi,

I'm looking for a (nice) way to connect std_logic_vector and several
std_logic in order to avoid modifying UCF files in ISE.

My simplified problem:
I have a top entity with two "inout" ports (let's say Data_0 and Data_1)
with type std_logic.
I want to map these two signals on an "inout" port of a component with
type std_logic_vector(1 downto 0).

My first idea was to use an alias, but I can't make it work. I tried
several ways:
- alias Data : std_logic_vector(1 downto 0) is (Data_0, Data_1);
- alias Data : std_logic_vector(1 downto 0) is (Data_0 & Data_1);
- alias Data : std_logic_vector(1 downto 0) is Data_0, Data_1;
- alias Data : std_logic_vector(1 downto 0) is Data_0 & Data_1;
ISE gives me an error in every case.

My second idea was to map directly.
port map ( Data => Data_0 & Data_1);
But ISE doesn't want to do that with inout ports.


For now, I'm lacking of ideas because I would really appreciate to solve
this issue without modifying my top entity.

Thanks in advance.
 
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Duane Clark
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      11-06-2007
Frédéric Lochon wrote:
>
> My second idea was to map directly.
> port map ( Data => Data_0 & Data_1);


port map ( Data(0) => Data_0, Data(1) => Data_1 );
 
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Tricky
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      11-08-2007
On Nov 6, 10:03 pm, Duane Clark <(E-Mail Removed)> wrote:
> Frédéric Lochon wrote:
>
> > My second idea was to map directly.
> > port map ( Data => Data_0 & Data_1);

>
> port map ( Data(0) => Data_0, Data(1) => Data_1 );


Or, maybe less elegent in the top level entity

signal temp_data : std_logic_vector(1 downto 0);
begin

temp_data <= data_1 & data_0;

--port map
data => temp_data,

 
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KJ
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      11-08-2007

"Tricky" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
On Nov 6, 10:03 pm, Duane Clark <(E-Mail Removed)> wrote:
> > Frédéric Lochon wrote:
> >
> > > My second idea was to map directly.
> > > port map ( Data => Data_0 & Data_1);

> >
> > port map ( Data(0) => Data_0, Data(1) => Data_1 );

>
> Or, maybe less elegent in the top level entity
>
> signal temp_data : std_logic_vector(1 downto 0);
> begin
>
> temp_data <= data_1 & data_0;
>
> --port map
> data => temp_data,


What you've suggested will only work if 'Data' is an input to the entity.

A similar (but reversed) approach of defining a temporary vector would work
if 'Data' was an output.

No such trick that I know of will work if 'Data' is an inout...mapping each
bit as Duane suggested will work in all situations.

KJ


 
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