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synthesis of 'X', 'Z', etc

 
 
Zerang Shah
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      02-03-2006
Hello,

std_logic can have the value '0' and '1' as well as 'X', 'Z', etc...

What are the synthesis consequences of case statements that include
'X', 'Z', etc? For example:

case some_bit is
when '1' =>
...
when '0' =>
...
when others =>
...
end case

Will most synthesis tools just ignore the "when others" part of the
statement? I'm guessing they do because I can't see a way to synthesize
'X' and 'Z' inputs, but I'm a noob so I could be wrong.

Thanks for the help.

 
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Ralf Hildebrandt
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      02-03-2006
Zerang Shah wrote:

> std_logic can have the value '0' and '1' as well as 'X', 'Z', etc...
>
> What are the synthesis consequences of case statements that include
> 'X', 'Z', etc?


If you assign 'Z' to a std_logic signal in some cases, it will be
synthesized to a tri-state buffer.
If you assign 'X' to a std_logic signal in some cases, it will be
threatened as don't care and logic reduction will be done.


> For example:
>
> case some_bit is
> when '1' =>
> ...
> when '0' =>
> ...
> when others =>
> ...
> end case


Because you have assigned a value for some_bit being '1' and '0' (this
means: for all valid cases) there are no cases left, that may appear in
the real world. -> The when others statement is ignored.

You can't test for 'Z' in the real world - a floating tri-state bus will
settle either to low or high.
You can't test for 'X' int he real world, because every signal will have
a value - but you only don't know which one.



An example for a tri-state driver:

sig1 <= data when sel(0)='1' else
'Z';

An example for logic reduction:

sig2 <= '1' when sel(1 downto 0)="00" else
'0' when sel(1 downto 0)="11" else
'X';


Ralf
 
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