ARRAY(n DOWNTO 0) OF STD_LOGIC_VECTOR(m DOWNTO 0) - VHDL

Hi,

I'm facing some dificulties when declaring an entity whit an array of std_logic_vector output port.

I want to develop a ping pong buffer with generic width and registers size.

I've tried three possibles "solutions" (but neither worked ) that are shown below with it's respective error messages:

possible solution 1:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ppbuffer IS -- ping pong buffer
	GENERIC (SIZE : INTEGER := 8;  -- buffer size
			 DATA : INTEGER := 8 ); -- registers size
	TYPE buff IS ARRAY (0 TO SIZE-1) OF STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
	PORT (enable, clk : IN STD_LOGIC;
		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
		  output : OUT buff);
END ppbuffer;

error for solution 1:

Error (10500): VHDL syntax error at ppbuffer.vhd(16) near text "PORT";  expecting "end", or "begin", or a declaration statement

possible solution 2:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE buff IS
	TYPE buff IS ARRAY (0 TO SIZE-1) OF STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
END buff;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.buff.all;

ENTITY ppbuffer IS -- ping pong buffer
	GENERIC (SIZE : INTEGER := 8;  -- buffer size
			 DATA : INTEGER := 8 ); -- data size
	PORT (enable, clk : IN STD_LOGIC;
		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
		  output : OUT buff);
END ppbuffer;

error for solution 2:

Error (10482): VHDL error at ppbuffer.vhd(5): object "SIZE" is used but not declared
Error (10482): VHDL error at ppbuffer.vhd(5): object "DATA" is used but not declared

possible solution 3:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE buff IS
	TYPE buff IS ARRAY ( NATURAL RANGE <>) OF STD_LOGIC_VECTOR ( NATURAL RANGE <>);
END buff;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.buff.all;

ENTITY ppbuffer IS -- ping pong buffer
	GENERIC (SIZE : INTEGER := 8;  -- buffer size
			 DATA : INTEGER := 8 ); -- data size
	PORT (enable, clk : IN STD_LOGIC;
		  input  : IN STD_LOGIC_VECTOR (DATA-1 DOWNTO 0);
		  output : OUT buff(0 TO SIZE-1)(DATA-1 DOWNTO 0));
END ppbuffer;

error for solution 3:

Error (10294): VHDL Type Declaration error at ppbuffer.vhd(5): element type for array type cannot be unconstrained

What I need is to declare a flexible port size buffer to use in a pipeline description that uses some buffers of different size. It's just like an std_logic_vector, but with vectors of std_logic inside it. I hope it's possible to describe in VHDL.

Any help would be appreciated

freitass