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Conditional module ports

 
 
M. Hamed
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      10-29-2007
I have a design that should accommodates two different packages with
some removed ports and internal modules for the smaller package. How
can I accomplish that with VHDL? I know I can use generate statements
to generate different logic conditionally, but how can I apply this to
the module ports?

Thank you.

 
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Andy
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      10-29-2007
On Oct 29, 1:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:
> I have a design that should accommodates two different packages with
> some removed ports and internal modules for the smaller package. How
> can I accomplish that with VHDL? I know I can use generate statements
> to generate different logic conditionally, but how can I apply this to
> the module ports?
>
> Thank you.


Can the larger one contain the smaller one (i.e big = small + extras)?
At least the "small" one would be common to both designs.

Lower level entities could have unused ports (declared on the entity
but not hooked up in the architecture and/or left open in the
instantiating architecture, with default values for inputs &
inouts)... So you could have two "wrapper" entities that contained the
same "main" entity, which is configured via generics, etc.

Andy

 
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M. Hamed
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Posts: n/a
 
      10-29-2007
Thanks for your suggestion. I need to synthesize this design and fit
it on an FPGA. I strongly think that the tool will complain if any
ports are unassigned!


On Oct 29, 12:02 pm, Andy <(E-Mail Removed)> wrote:
> On Oct 29, 1:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:
>
> > I have a design that should accommodates two different packages with
> > some removed ports and internal modules for the smaller package. How
> > can I accomplish that with VHDL? I know I can use generate statements
> > to generate different logic conditionally, but how can I apply this to
> > the module ports?

>
> > Thank you.

>
> Can the larger one contain the smaller one (i.e big = small + extras)?
> At least the "small" one would be common to both designs.
>
> Lower level entities could have unused ports (declared on the entity
> but not hooked up in the architecture and/or left open in the
> instantiating architecture, with default values for inputs &
> inouts)... So you could have two "wrapper" entities that contained the
> same "main" entity, which is configured via generics, etc.
>
> Andy



 
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Andy
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Posts: n/a
 
      10-29-2007
On Oct 29, 4:44 pm, "M. Hamed" <(E-Mail Removed)> wrote:
> Thanks for your suggestion. I need to synthesize this design and fit
> it on an FPGA. I strongly think that the tool will complain if any
> ports are unassigned!
>
> On Oct 29, 12:02 pm, Andy <(E-Mail Removed)> wrote:
>
> > On Oct 29, 1:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:

>
> > > I have a design that should accommodates two different packages with
> > > some removed ports and internal modules for the smaller package. How
> > > can I accomplish that with VHDL? I know I can use generate statements
> > > to generate different logic conditionally, but how can I apply this to
> > > the module ports?

>
> > > Thank you.

>
> > Can the larger one contain the smaller one (i.e big = small + extras)?
> > At least the "small" one would be common to both designs.

>
> > Lower level entities could have unused ports (declared on the entity
> > but not hooked up in the architecture and/or left open in the
> > instantiating architecture, with default values for inputs &
> > inouts)... So you could have two "wrapper" entities that contained the
> > same "main" entity, which is configured via generics, etc.

>
> > Andy


You may get warnings if ports on internal modules are not assigned (as
long as it is legal vhdl: in/inout ports, if left open, must have been
declared with default values, etc.), but otherwise it will be ok.

If you have ports that are not driven/used in the top level
architecture, then you will get errors...

Andy

 
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KJ
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Posts: n/a
 
      10-29-2007

"M. Hamed" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Thanks for your suggestion. I need to synthesize this design and fit
> it on an FPGA. I strongly think that the tool will complain if any
> ports are unassigned!
>

You're mistaken. Outputs can always be left unconnected, inputs and inouts
can be left unconnected if the entity defines a default value for the
signal. Works for simulation and synthesis. If your synthesis tool
complains you have a bad tool, get a better one.

Ex:

entity foo is port(
Some_Input: std_logic; -- No default, must connect
Some_Input2: std_logic := '0'; -- Can leave left open
Some_Output: std_logic);
end foo;

One possible instantiation is...
My_Foo : entity work.foo port map(Some_Input => Some_Signal);


KJ


 
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Uncle Noah
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Posts: n/a
 
      10-30-2007
On Oct 29, 8:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:
> I have a design that should accommodates two different packages with
> some removed ports and internal modules for the smaller package. How
> can I accomplish that with VHDL? I know I can use generate statements
> to generate different logic conditionally, but how can I apply this to
> the module ports?
>
> Thank you.


Hi

"conditional" is the magic word for you. You need not (or you better
not) mess with tricks to create the effect of conditional ports. It is
simpler to preprocess your VHDL source code via (e.g.) the "kpp"
preprocessor or something equivalent.

Nikolaos Kavvadias

 
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Thomas Stanka
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      10-30-2007
On 30 Okt., 03:46, Uncle Noah <(E-Mail Removed)> wrote:
> On Oct 29, 8:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:
>
> > I have a design that should accommodates two different packages with
> > some removed ports and internal modules for the smaller package. How
> > can I accomplish that with VHDL? I know I can use generate statements
> > to generate different logic conditionally, but how can I apply this to
> > the module ports?

>
> > Thank you.

>
> "conditional" is the magic word for you. You need not (or you better
> not) mess with tricks to create the effect of conditional ports. It is
> simpler to preprocess your VHDL source code via (e.g.) the "kpp"
> preprocessor or something equivalent.




I Disagree. In my opinion it is better to use configurations and
generics than preprocessors. This is valid vhdl, so every tool knows
how to handle them.
OK, made a joke s/every tool/every good tool/.

bye Thomas

 
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KJ
Guest
Posts: n/a
 
      10-30-2007

"Thomas Stanka" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ps.com...
> On 30 Okt., 03:46, Uncle Noah <(E-Mail Removed)> wrote:
>> On Oct 29, 8:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:
>>
>> > I have a design that should accommodates two different packages with
>> > some removed ports and internal modules for the smaller package. How
>> > can I accomplish that with VHDL? I know I can use generate statements
>> > to generate different logic conditionally, but how can I apply this to
>> > the module ports?

>>
>> > Thank you.

>>
>> "conditional" is the magic word for you. You need not (or you better
>> not) mess with tricks to create the effect of conditional ports. It is
>> simpler to preprocess your VHDL source code via (e.g.) the "kpp"
>> preprocessor or something equivalent.

>
>
>
> I Disagree. In my opinion it is better to use configurations and
> generics than preprocessors. This is valid vhdl, so every tool knows
> how to handle them.
> OK, made a joke s/every tool/every good tool/.
>
> bye Thomas
>


You're both making this harder than it needs to be with pre-processors (bad
since it goes outside the language) and configuration statements (not needed
and possibly not well supported for synthesis...haven't checked on this
lately though). The poster was simply asking about not connecting signals
to a given entity because that particular instantiation does not support all
of the bells and whistles that another instantiation might. There is no
need for anything conditional about the entity itself, there can be
conditional logic (via the generate) if needed in the instantiation of that
entity.

KJ


 
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Andy
Guest
Posts: n/a
 
      10-30-2007
On Oct 30, 6:20 am, "KJ" <(E-Mail Removed)> wrote:
> "Thomas Stanka" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed) ps.com...
>
>
>
> > On 30 Okt., 03:46, Uncle Noah <(E-Mail Removed)> wrote:
> >> On Oct 29, 8:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:

>
> >> > I have a design that should accommodates two different packages with
> >> > some removed ports and internal modules for the smaller package. How
> >> > can I accomplish that with VHDL? I know I can use generate statements
> >> > to generate different logic conditionally, but how can I apply this to
> >> > the module ports?

>
> >> > Thank you.

>
> >> "conditional" is the magic word for you. You need not (or you better
> >> not) mess with tricks to create the effect of conditional ports. It is
> >> simpler to preprocess your VHDL source code via (e.g.) the "kpp"
> >> preprocessor or something equivalent.

>
> > I Disagree. In my opinion it is better to use configurations and
> > generics than preprocessors. This is valid vhdl, so every tool knows
> > how to handle them.
> > OK, made a joke s/every tool/every good tool/.

>
> > bye Thomas

>
> You're both making this harder than it needs to be with pre-processors (bad
> since it goes outside the language) and configuration statements (not needed
> and possibly not well supported for synthesis...haven't checked on this
> lately though). The poster was simply asking about not connecting signals
> to a given entity because that particular instantiation does not support all
> of the bells and whistles that another instantiation might. There is no
> need for anything conditional about the entity itself, there can be
> conditional logic (via the generate) if needed in the instantiation of that
> entity.
>
> KJ


KJ, that is correct as far as it goes. But he also has different IO at
the top level based on which design and which FPGA package he is
targeting. For synthesis there is no "instantiation" of the top level
entity, so it is not a matter of leaving ports open in a port map. If
he were to use the "superset" top level entity, and just not attach to
some of the ports in the top level architecture, that would generate
errors in most synthesis tools.

Lower level entities can have portions of their port maps left open
(under the rules of vhdl), and only generate warnings (if that) in a
synthesis tool. I don't see a good way of escaping having two
different top level entities (and their architectures). But the top
level architectures could instantiate the same lower level entity
(with one having some open port associations). In addition, a generic
or three could be passed to that entity to alter the internal
construction (i.e. lower level modules either left out or included).

Depending on how bad you want to have a single entity, there are some
ugly, but pure-vhdl solutions. One is to have all the IO defined as a
record, whose definition is in a package. Change the package, change
the port definitions. You can have a single record port of mode inout,
or three separate record ports of modes in, out, and inout
respectively. Beware that synthesis tools are not usually very kind
in intelligently renaming record elements into pin names.

Another related option is to combine all the IO into one (or three)
std_logic_vectors whose widths are constrained by three generics (top
level generics can be set via tool (or command-line) option during
synthesis and/or simulation. Keeping track of the bit-mapping of
individual IOs in the vectors would best be handled by named constants
in a package, or by conversion to/from a record via one or more
functions in a package (the function can be overloaded based on the
width of the vector or the type of the record). But when you are
looking at a PAR report, all the ports are just going to be numbered,
and you'll have to manually convert to individual port names.

Both of these latter options are really ugly, but IMHO, better that
resorting to a non-standard preprocessor.

Andy

 
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M. Hamed
Guest
Posts: n/a
 
      10-30-2007
Thanks All for the suggestions, and thanks Andy for summing up the
whole issue. I do believe the synthesis tool will generate errors if
ports at the top level are more than the target FPGA package can
handle. I think I will go with the two entities (two architectures?)
approach. It makes it easier to understand and maintain. I agree the
other two options are ugly however I don't totally agree they're
better than a preprocessor. I think a built-in VHDL preprocessor that
is recognized by the synthesis tool would have made my life easier.
After all this is a medium size VHDL project after which my group
management decided to switch to Verilog. It doesn't really pay to
strictly adhere to VHDL standard and conceptions when getting the job
done is more important. Using an external preprocessor is a bit messy
for me since it means running another tool before the synthesis tool
is invoked .. yikes!



On Oct 30, 6:14 am, Andy <(E-Mail Removed)> wrote:
> On Oct 30, 6:20 am, "KJ" <(E-Mail Removed)> wrote:
>
>
>
> > "Thomas Stanka" <(E-Mail Removed)> wrote in message

>
> >news:(E-Mail Removed) ups.com...

>
> > > On 30 Okt., 03:46, Uncle Noah <(E-Mail Removed)> wrote:
> > >> On Oct 29, 8:18 pm, "M. Hamed" <(E-Mail Removed)> wrote:

>
> > >> > I have a design that should accommodates two different packages with
> > >> > some removed ports and internal modules for the smaller package. How
> > >> > can I accomplish that with VHDL? I know I can use generate statements
> > >> > to generate different logic conditionally, but how can I apply this to
> > >> > the module ports?

>
> > >> > Thank you.

>
> > >> "conditional" is the magic word for you. You need not (or you better
> > >> not) mess with tricks to create the effect of conditional ports. It is
> > >> simpler to preprocess your VHDL source code via (e.g.) the "kpp"
> > >> preprocessor or something equivalent.

>
> > > I Disagree. In my opinion it is better to use configurations and
> > > generics than preprocessors. This is valid vhdl, so every tool knows
> > > how to handle them.
> > > OK, made a joke s/every tool/every good tool/.

>
> > > bye Thomas

>
> > You're both making this harder than it needs to be with pre-processors (bad
> > since it goes outside the language) and configuration statements (not needed
> > and possibly not well supported for synthesis...haven't checked on this
> > lately though). The poster was simply asking about not connecting signals
> > to a given entity because that particular instantiation does not support all
> > of the bells and whistles that another instantiation might. There is no
> > need for anything conditional about the entity itself, there can be
> > conditional logic (via the generate) if needed in the instantiation of that
> > entity.

>
> > KJ

>
> KJ, that is correct as far as it goes. But he also has different IO at
> the top level based on which design and which FPGA package he is
> targeting. For synthesis there is no "instantiation" of the top level
> entity, so it is not a matter of leaving ports open in a port map. If
> he were to use the "superset" top level entity, and just not attach to
> some of the ports in the top level architecture, that would generate
> errors in most synthesis tools.
>
> Lower level entities can have portions of their port maps left open
> (under the rules of vhdl), and only generate warnings (if that) in a
> synthesis tool. I don't see a good way of escaping having two
> different top level entities (and their architectures). But the top
> level architectures could instantiate the same lower level entity
> (with one having some open port associations). In addition, a generic
> or three could be passed to that entity to alter the internal
> construction (i.e. lower level modules either left out or included).
>
> Depending on how bad you want to have a single entity, there are some
> ugly, but pure-vhdl solutions. One is to have all the IO defined as a
> record, whose definition is in a package. Change the package, change
> the port definitions. You can have a single record port of mode inout,
> or three separate record ports of modes in, out, and inout
> respectively. Beware that synthesis tools are not usually very kind
> in intelligently renaming record elements into pin names.
>
> Another related option is to combine all the IO into one (or three)
> std_logic_vectors whose widths are constrained by three generics (top
> level generics can be set via tool (or command-line) option during
> synthesis and/or simulation. Keeping track of the bit-mapping of
> individual IOs in the vectors would best be handled by named constants
> in a package, or by conversion to/from a record via one or more
> functions in a package (the function can be overloaded based on the
> width of the vector or the type of the record). But when you are
> looking at a PAR report, all the ports are just going to be numbered,
> and you'll have to manually convert to individual port names.
>
> Both of these latter options are really ugly, but IMHO, better that
> resorting to a non-standard preprocessor.
>
> Andy



 
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