Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > 8-bit to 32-bit expansion

Reply
Thread Tools

8-bit to 32-bit expansion

 
 
Vagant
Guest
Posts: n/a
 
      10-24-2007
Hello All,

I am interested how to design interface between parallel port of PC
and FPGA-based device which has to have 16-bit data bus and 16-bit
address bus. Thus, I have a problem how to expand 8 data lines of a
parallel
port into 32 bit bus. How such interface can be described in VHDL?

 
Reply With Quote
 
 
 
 
Pascal Peyremorte
Guest
Posts: n/a
 
      10-24-2007
Vagant a écrit :
> Hello All,
>
> I am interested how to design interface between parallel port of PC
> and FPGA-based device which has to have 16-bit data bus and 16-bit
> address bus. Thus, I have a problem how to expand 8 data lines of a
> parallel
> port into 32 bit bus. How such interface can be described in VHDL?
>

Is it a school exercice ?
Let you to use 4 latches selected by 2 adresses lines
 
Reply With Quote
 
 
 
 
Vagant
Guest
Posts: n/a
 
      10-26-2007
On Oct 24, 10:13 am, Pascal Peyremorte
<(E-Mail Removed)> wrote:
> Vagant a écrit :> Hello All,
>
> > I am interested how to design interface between parallel port of PC
> > and FPGA-based device which has to have 16-bit data bus and 16-bit
> > address bus. Thus, I have a problem how to expand 8 data lines of a
> > parallel
> > port into 32 bit bus. How such interface can be described in VHDL?

>
> Is it a school exercice ?
> Let you to use 4 latches selected by 2 adresses lines


It is not a school exercise. Using 4 latches with 2 address lines
doesn't make much sense to me until it explained in detail. How you
propose to connect them
in order to achieve building a 32-bit bus as an output?

 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      10-26-2007
Vagant schrieb:

> I am interested how to design interface between parallel port of PC
> and FPGA-based device which has to have 16-bit data bus and 16-bit
> address bus.


=> You need a Port Control Component, that handles bus communication via
the parallel port.
=> You need a state machine or CPU that is connected to this Port
Control Component and that does something with the transmitted data.


> How such interface can be described in VHDL?


Read the documentation of commercial IP cores how they can be interfaced
to state machines / CPUs to have an idea, what job the Port Control
Component has to do.

Often such peripheral components are connected using an asynchronous RAM
interface. (address bus, data bus (in and out), chip select, write enable)

Ralf
 
Reply With Quote
 
Vagant
Guest
Posts: n/a
 
      10-26-2007
On Oct 26, 3:36 pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
> Vagant schrieb:
>
> > I am interested how to design interface between parallel port of PC
> > and FPGA-based device which has to have 16-bit data bus and 16-bit
> > address bus.

>
> => You need a Port Control Component, that handles bus communication via
> the parallel port.
> => You need a state machine or CPU that is connected to this Port
> Control Component and that does something with the transmitted data.
>
> Ralf


Thank you.
Has this Port Control Component to be a separate PCB or it can be FPGA-
based?


 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      10-26-2007
Vagant schrieb:


> Has this Port Control Component to be a separate PCB or it can be FPGA-
> based?


As you wish. Usually such a component is used as a subcomponent inside a
bigger design inside the FPGA.


For beginners I recommend to simulate, simulate, simulate and then
finally take an FPGA. Chose a small and easy example.

Ralf
 
Reply With Quote
 
Vagant
Guest
Posts: n/a
 
      10-27-2007
On Oct 26, 7:54 pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
> Vagant schrieb:
>
> > Has this Port Control Component to be a separate PCB or it can be FPGA-
> > based?

>
> As you wish. Usually such a component is used as a subcomponent inside a
> bigger design inside the FPGA.
>
> For beginners I recommend to simulate, simulate, simulate and then
> finally take an FPGA. Chose a small and easy example.
>
> Ralf


Yes, I am struggling with this..but hope my simple design will get
working one day! The most difficult thing is to get the key concept
about such 8-bit->32-bit expansion. At the moment I still have not
understood that. But I've no new question anyway.. I will just reflect
on whole situation for a while and try to make my simple design
working.

 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      10-28-2007
Vagant schrieb:

> The most difficult thing is to get the key concept
> about such 8-bit->32-bit expansion.


No, this is not your problem. Vector width expansion is easy:

use IEEE.Numeric_std.all;

signal vec32 : std_ulogic_vector(31 downto 0);
signal vec8 : std_ulogic_vector(7 downto 0);

vec32<=std_ulogic_vector(resize(unsigned(vec,vec 32'length));
-- or
vec32<=std_ulogic_vector(resize( signed(vec,vec32'length));


Your problem is (1) data transfer from the FPGA to the PC and (2) access
of the transferred data inside the FPGA.


Ralf
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Expansion of the Sun X-Terminal Mod bigal Case Modding 85 11-07-2008 11:02 AM
Wireless network and Age of Empires Expansion multiplayer =?Utf-8?B?Qm9iIFcu?= Wireless Networking 1 04-05-2005 07:31 PM
Tilde Expansion MB2 ASP .Net 1 09-24-2004 08:45 PM
1721 expansion Can2002 Cisco 2 11-29-2003 07:39 PM
questions - network expansion - x3500-xl GigaStack vs G5483 1000BaseT - 3550-12T vs 3750G-24TS Joel M. Baldwin Cisco 3 10-25-2003 05:14 PM



Advertisments