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ModelSim Verilog problem with simple simulation

 
 
bbiandov bbiandov is offline
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Join Date: Sep 2006
Posts: 17
 
      10-20-2007
Hi

I'm trying to do the simplest of things - to run the counter.v and tcounter.v simulation and create a waveform. However once compiled, I have no objects hence nothing that can be added to the waveform. I get no errors at all, just no objects after I compile. I see the two files under my library, I can click ont he testbench file and it opens in SIM but objects window is just empty. Attempting to add to waveform casues error - no objects found?

The funny thing is that if I compile the exact same design and testbench but use the vhdl versions, then I do have objects available to add to a waveform.

What gives? Are the Verilog examples counter.v and tcounter.v screwed? They came from the original distribution and most of all - I get to compile them with no errors?

Thanks
~B
 
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scottcarl scottcarl is offline
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Join Date: May 2007
Location: USA
Posts: 51
 
      10-22-2007
bbiandov,

It sounds like you don't have the Verilog license, only the VHDL. Modelsim will allow you to compile any type of code(VHDL or Verilog) but you must purchase the Verilog simulator license if you want to see the signals. I hope you've got a couple thousand spare dollars for it. Check out Aldec Active-HDL for a better mixed mode simulator than Modelsim. ($5000 for mixed language mode).

Scott
 
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bbiandov bbiandov is offline
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Join Date: Sep 2006
Posts: 17
 
      10-22-2007
Found the problem - disable optimization. Then all objects show up..

VoptFlow = 0 in modelsim.ini

~B
 

Last edited by bbiandov; 10-22-2007 at 10:54 PM..
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