access internal signal on top level in VHDL

01-27-2006

hi,
i want to force a value or read a value of an internal signal in VHDL .
That is possible with signal spy in model sim but i want to use ncsim .
Is it possible with ncsim without using any other language's interface
(like c or tcl)??
please suggest

01-27-2006

NC has similar feature called NC_MIRROR. You may also want to look at a
small package that we wrote a while back to work seamlessly across
simulators. I'm updating ti for VCSMX soon, but the one that works with
MTI/NC/Aldec is @

http://www.noveldv.com/eda/probe.zip

HTH
Ajeetha
www.noveldv.com

01-27-2006

anupam wrote:

> i want to force a value or read a value of an internal signal in VHDL .
> That is possible with signal spy in model sim but i want to use ncsim .
> Is it possible with ncsim without using any other language's interface
> (like c or tcl)??

Its possible to do this with only plain VHDL:
http://groups.google.de/group/comp.l...232b67411adef8

Ralf

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