Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > access internal signal on top level in VHDL

Reply
Thread Tools

access internal signal on top level in VHDL

 
 
anupam
Guest
Posts: n/a
 
      01-27-2006
hi,
i want to force a value or read a value of an internal signal in VHDL .
That is possible with signal spy in model sim but i want to use ncsim .
Is it possible with ncsim without using any other language's interface
(like c or tcl)??
please suggest

 
Reply With Quote
 
 
 
 
Ajeetha
Guest
Posts: n/a
 
      01-27-2006
NC has similar feature called NC_MIRROR. You may also want to look at a
small package that we wrote a while back to work seamlessly across
simulators. I'm updating ti for VCSMX soon, but the one that works with
MTI/NC/Aldec is @

http://www.noveldv.com/eda/probe.zip

HTH
Ajeetha
www.noveldv.com

 
Reply With Quote
 
 
 
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      01-27-2006
anupam wrote:

> i want to force a value or read a value of an internal signal in VHDL .
> That is possible with signal spy in model sim but i want to use ncsim .
> Is it possible with ncsim without using any other language's interface
> (like c or tcl)??


Its possible to do this with only plain VHDL:
http://groups.google.de/group/comp.l...232b67411adef8

Ralf
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Assignment to output signal from internal signal not istantaneous dibacco73 VHDL 1 02-12-2009 11:28 PM
In VHDL testbench, how do I probe internal signal of an entity? G Iveco VHDL 6 07-23-2007 09:19 AM
access internal signal in VHDL from verilog tkvhdl@gmail.com VHDL 4 06-27-2007 08:13 PM
Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal Weng Tianxiang VHDL 2 01-30-2007 12:58 PM
c is a low-level language or neither low level nor high level language pabbu C Programming 8 11-07-2005 03:05 PM



Advertisments