Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > General Computer Discussion > Hardware > DC_SHELL, synopsys

Reply
Thread Tools

DC_SHELL, synopsys

 
 
perseo perseo is offline
Junior Member
Join Date: Oct 2007
Posts: 3
 
      10-11-2007
Hi everybody,

Iīm working with Synopsys and my problem is my experiments donīt fit to theory. Iīm measuring power and I donīt know what is failing if anything is really failing.

Well, power is divided in two components
1) Static
2) Dynamic. And dynamic power is also divided in two components:
2.1) Net switching power, due to charge and discharge of output capacitance
2.2) Cell internal power

Well, according to synopsys' (and I think everybody's) theory, net switching is more or less 90% of dynamic power, while cell internal power could reach a 30% peak in circuits with few transitions.

However, my results are

Global Operating Voltage = 2.5
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000ff
Time Units = 1ps
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1mW


Cell Internal Power = 644.8631 nW (66%)
Net Switching Power = 329.3489 nW (34%)
---------
Total Dynamic Power = 974.2120 nW (100%)

Cell Leakage Power = 33.4626 nW


Iīm using two scripts for achieving power results.

1)

power_preserve_rtl_hier_names = true
analyze -format vhdl -lib WORK "./prueba.vhd"
elaborate prueba -arch "beh1" -lib WORK -update
rtl2saif -output "prueba.RT.saif" -design "prueba"
compile
derive_timing_constraints

2)

sh "vcd2saif -i prueba.vcd -o prueba.saif -rtl prueba.RT.saif -strip prueba"
elaborate prueba -arch "beh1" -lib WORK -update
compile
read_saif -input prueba.saif -instance top
report_power
report_area
report_timing
report_clock

Well, the .vcd file (stimulus file) is obtained by simulating values with modelsim.

One thing Iīve tried is varying bit by bit the inputs in the macro of modelsim, but I only get an increase of 15 nW in net switching power, what is very little.

I donīt know what is happening. Any idea ??

Thank you a lot
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
will Synopsys Design Compiler automatically collect common sub expression to do intelligent optimization? walala VHDL 6 09-25-2003 11:43 AM
Am I right in my VHDL code? Synopsys DC runs for ever... walala VHDL 8 09-24-2003 02:04 PM
NEWBIE ASKING FOR HELP! can anybody take a look at my Synopsys DC report? walala VHDL 2 09-13-2003 04:23 PM
SOS! What can I do if Synopsys does not allow my statement? walala VHDL 1 09-12-2003 09:10 PM



Advertisments