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How in Design Compiler disable writing out "Assign" statement into the netlist?

 
 
Frank
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      01-20-2006
I was aware that there is a flag which can disenable Design Compiler to
write Assign statement. My NCVerilog gave me warning on Assign statement
when performing gate level simulations.

Many thanks in advance.



 
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Ajeetha
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      01-22-2006
Frank,
See:

http://www.deepchip.com/posts/0184.html

HTH
Ajeetha
www.noveldv.com

 
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Jerry Avins
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      01-22-2006
Ajeetha wrote:
> Frank,
> See:
>
> http://www.deepchip.com/posts/0184.html
>
> HTH
> Ajeetha
> www.noveldv.com


I love this quote: "It's always been my dream to give my customers a
choice between ViewLogic & ViewLogic." That's a nice perch to sit on!

Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
 
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