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VHDL - Synthesis erron for "bit'val" attribute....plz chek

 
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Old 01-19-2006, 12:51 PM   #1
Default Synthesis erron for "bit'val" attribute....plz chek


hi all i am using this function to convetr integer to bitvector and
Synplify gives error

pack.vhd(25): type bit needs a syn_enum_encoding attribute of
"sequential" @E:"c:\synthesis\one\pack.vhd":25:22:25:29

code is here:- please have a look
-------------------------------------------------------------------
PACKAGE convert is
function int_to_bv(int : in integer) return bit_vector;
END convert;
PACKAGE BODY convert is

function int_to_bv(int : in integer) return bit_vector is
variable temp : integer;
variable result : bit_vector(0 to 8-1);

begin
if int < 0 then
temp := -(int+1);
else
temp := int;
end if;
for index in result'reverse_range loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
if int < 0 then
result := not result;
result(result'left) := '1';
end if;
return result;
end int_to_bv;
end convert;
-------------------------------------------------------------
best regards,
mirza



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Old 01-19-2006, 03:10 PM   #2
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Default Re: Synthesis erron for "bit'val" attribute....plz chek
Thanks every one, I got that "rem" is not supported by synthesis.



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