http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

> hi,

>

> I have this code (pseudo code, all inputs and signal should be unsigned

> integers):

>

> input first_input, second_input: std_logic_vector (4 downto 0);

>

> Library IEEE;

> use IEEE.std_logic_1164.all;

> use IEEE.std_logic_arith.all;

> use IEEE.std_logic_unsigned.all;

>

> signal total : std_logic_vector (5 downto 0);

> get_total : process (my_inputs)

> begin -- process

> total <= '0' & (("11110" - first_input) + ("11110" -

> second_input));

> end process;

>

> that is, total = (30 - first input) + (30 -second_input).

>

> When first_input and second_input are both zero total comes equal to 28

> decimal, not 60,

> with modelsim. What am i doing wrong? Bad libraries, bad signal types,

> what? I have experience

> with Verilog, but not vhdl....

>

> Thanks,

> Mon

>
Consider, 28 = 60 - 32

You have lost the top bit. Reason: your intermediate results are still

of type std_logic_vector(4 downto 0), ie 5 bits. So 60 (111100 binary)

gets truncated to fit.

Try this:

input first_input, second_input: std_logic_vector (4 downto 0);

Library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

signal total : std_logic_vector (5 downto 0);

get_total : process (my_inputs)

variable a, b : std_logic_vector (5 downto 0);

begin -- process

a := '0' & first_input; -- prepend zero to each

b := '0' & second_input;

-- again, prepending zero to the consts.

total <= ("011110" - a) + ("011110" - b);

end process;