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VHDL - very large no. of interconnections |
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Hi,
I want to have some arbitrary number of instanstiations and the interconnection are not in regular fashion( there is no fixed relationship to derive interconnections).. Can anybody tell how to make for eg. generate genvar i; for(i=0;i<=15;i=i+1) //Lowest level L1 begin:rout1 di #(.INPUT_WIDTH( (4 + L2)), .OUTPUT_WIDTH((4 + L2)) , .ADDR_BIT_WIDTH(ADDR_BIT_WIDTH) ) ) d1_dut_11( .clk(clk), .reset(reset), .data_in1(data_temp2[i]) .data_in2(data_temp5[i]) .data_in3(data_temp6[i]) ); end endgenerate My problem: In port map(named association) I must have some arbirary way of connections. So its really difficult to derive from genvar i. I am planning to use 1.some function call to map into this arbitrary way. eg ..data_in1(data_temp2[map_fun(i)]) 2. Use some array to use its .data_in1(data_temp2[map_arr[i]]) Is it possible to do this or is there any other smart way? Please let me know... --Junaid junaid.ece@gmail.com |
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