Generic design using generate statement

Hi,

I want to have a very high generic model. For that I instantiate no. of
modules in a generic way. And I need generic number of interconnecting
to make connection between these modules..

So Can I make the declaration in generic way using generate statement.?
To be specific, can I use generate statement for declaration of
variables..?

Please relpy me...

Junaid

junaid.ece@gmail.com

wrote:

> So Can I make the declaration in generic way using generate statement.?
> To be specific, can I use generate statement for declaration of
> variables..?

Variables are declared inside the process,
but variable types can use generic constants
for any dimension of the structure.

See the how the generic char_len_c
is used in the reference design here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

Mike Treseler

Mike Treseler wrote:
> wrote:
>
> > So Can I make the declaration in generic way using generate statement.?
> > To be specific, can I use generate statement for declaration of
> > variables..?
>
> Variables are declared inside the process,
> but variable types can use generic constants
> for any dimension of the structure.
>
> See the how the generic char_len_c
> is used in the reference design here:
>
> http://home.comcast.net/~mike_treseler/
>
> -- Mike Treseler

Hi Mike,

Thank you for your reply.

I am basically dealing with SystemVerilog and want to have generic
interconnecting wires..

--Junaid

junaid.ece@gmail.com

<> wrote in message news: oups.com...
>
> Mike Treseler wrote:
>> wrote:
>>
>> > So Can I make the declaration in generic way using generate statement.?
>> > To be specific, can I use generate statement for declaration of
>> > variables..?
>>
>> Variables are declared inside the process,
>> but variable types can use generic constants
>> for any dimension of the structure.
>>
>> See the how the generic char_len_c
>> is used in the reference design here:
>>
>> http://home.comcast.net/~mike_treseler/
>>
>> -- Mike Treseler
>
> Hi Mike,
>
> Thank you for your reply.
>
> I am basically dealing with SystemVerilog and want to have generic
> interconnecting wires..

If you need help with System Verilog, try comp.lang.verilog.

If you need to turn System Verilog into a VHDL design, then
'generate' statements in SV work pretty similar to VHDL generate statements.

You 'generate' concurrent statements, which means you can declare 'signals'
and processes (with variables) under a generate statement.

Rob

>
> --Junaid
>

Rob Dekker