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Answer: maximum number of state machines in a current chip: > 500k

 
 
Weng Tianxiang
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      09-22-2007
Hi,
Here is the answer to the maximum number of state machines in a
current chip: > 500k.

My original answer posing has some errors.

1. It is L2 cache that uses a lot of state machines;
http://en.wikipedia.org/wiki/Cache_coherence

2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
and
Invalid);
http://en.wikipedia.org/wiki/MESI_protocol


3. Please visit Intel product website to get the latest news:
http://download.intel.com/products/p..._prodbrief.pdf


4. "with up to 8 MB of L2 cache per processor" and 4 processors.
It means 4*8MB = 32MB L2 cache;

5. L2 cache is divided into data L2 cache and instruction L2 cache and
only data L2 cache uses MESI protocol.

6. Each 32Bytes is a cache line;

7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
machines using MESI protocol.

8. L1/L3 cache and instruction L2 cache use several independent 1-bit
flip-flops to recode their states so that they are not counted as
state machines.

The final answer is:
There is at least 500k state machines in Intel chip.

a. It is available to every users in the topics groups;
b. They are written in Verilog, not in VHDL;
c. FPGA has never had a design using L2 cache.

Weng

 
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Jonathan Bromley
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      09-22-2007
On Sat, 22 Sep 2007 07:49:35 -0700,
Weng Tianxiang <(E-Mail Removed)> wrote:
>The final answer is:
>There is at least 500k state machines in Intel chip.


>a. It is available to every users in the topics groups;

Likewise, the mediaeval discussions about how many angels
can dance on the head of a pin are accessible to all.
In both cases, most of us don't care.

>b. They are written in Verilog, not in VHDL;

Utterly unimportant, and possibly not even true.
Intel uses a range of proprietary in-house tools
and languages in addition to Verilog.

>c. FPGA has never had a design using L2 cache.

Even if that is true, I defy you to prove it.
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
http://www.velocityreviews.com/forums/(E-Mail Removed)
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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John Retta
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      09-22-2007
Which leads us to another interesting question ....

What are the maximium number of lemons that
the human mind can imagine being rotated
simultaneously?

[Please note the lemons can not be bruised.
This is a degenerate case that the theorem does
not apply]

--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

email : (E-Mail Removed)
web : www.rtc-inc.com


"Weng Tianxiang" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>
> 1. It is L2 cache that uses a lot of state machines;
> http://en.wikipedia.org/wiki/Cache_coherence
>
> 2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
> and
> Invalid);
> http://en.wikipedia.org/wiki/MESI_protocol
>
>
> 3. Please visit Intel product website to get the latest news:
> http://download.intel.com/products/p..._prodbrief.pdf
>
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>
> 5. L2 cache is divided into data L2 cache and instruction L2 cache and
> only data L2 cache uses MESI protocol.
>
> 6. Each 32Bytes is a cache line;
>
> 7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
> machines using MESI protocol.
>
> 8. L1/L3 cache and instruction L2 cache use several independent 1-bit
> flip-flops to recode their states so that they are not counted as
> state machines.
>
> The final answer is:
> There is at least 500k state machines in Intel chip.
>
> a. It is available to every users in the topics groups;
> b. They are written in Verilog, not in VHDL;
> c. FPGA has never had a design using L2 cache.
>
> Weng
>



 
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Evan Lavelle
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      09-22-2007
At last - something interesting in this thread.

On Sat, 22 Sep 2007 17:37:19 +0100, Jonathan Bromley
<(E-Mail Removed)> wrote:

>On Sat, 22 Sep 2007 07:49:35 -0700,
>Weng Tianxiang <(E-Mail Removed)> wrote:
>>The final answer is:
>>There is at least 500k state machines in Intel chip.


Why? Wouldn't the smart thing be to build *one* cache coherency
controller in your chip, and to save your 2 state bits as two extra
bits in the 256 memory bits in your cache block?

>>a. It is available to every users in the topics groups;

>Likewise, the mediaeval discussions about how many angels
>can dance on the head of a pin are accessible to all.
>In both cases, most of us don't care.


Actually, to the religiously inclined (among whose number I am not,
alas, to be counted) this is potentially a very interesting question.
The debate was actually about whether or not Angels had a corporeal
existence; the title was just whimsy. Thomas Aquinas's answer, for the
case of a pinhead which was a geometrical point, was, I think, 'one'.

So, maybe there was something fundamental we missed in the original
question. Was it just an allegory? One FSM, one Angel. Spooky.
 
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neilla@pipstechnology.co.uk
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      09-24-2007
On 22 Sep, 15:49, Weng Tianxiang <(E-Mail Removed)> wrote:
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>


And there is also one more big error.

> 3. Please visit Intel product website to get the latest news:http://download.intel.com/products/p..._prodbrief.pdf
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>


If you read the product brief again, you should see that there is only
8MB of L2 on the whole chip. This is split into 2 sets of 4MB which
can then be accessed by 2 cores. Where Intel says processor they are
referring to the whole chip, and core is used to refer to the 4
processors on the chip.

 
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Mike Lewis
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Posts: n/a
 
      09-24-2007

"Weng Tianxiang" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>
> 1. It is L2 cache that uses a lot of state machines;
> http://en.wikipedia.org/wiki/Cache_coherence
>
> 2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
> and
> Invalid);
> http://en.wikipedia.org/wiki/MESI_protocol
>
>
> 3. Please visit Intel product website to get the latest news:
> http://download.intel.com/products/p..._prodbrief.pdf
>
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>
> 5. L2 cache is divided into data L2 cache and instruction L2 cache and
> only data L2 cache uses MESI protocol.
>
> 6. Each 32Bytes is a cache line;
>
> 7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
> machines using MESI protocol.
>
> 8. L1/L3 cache and instruction L2 cache use several independent 1-bit
> flip-flops to recode their states so that they are not counted as
> state machines.
>
> The final answer is:
> There is at least 500k state machines in Intel chip.
>
> a. It is available to every users in the topics groups;
> b. They are written in Verilog, not in VHDL;
> c. FPGA has never had a design using L2 cache.
>
> Weng
>


saying that there are more than 500K state machines has not stated what the
maximum number can be.


 
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ghelbig@lycos.com
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Posts: n/a
 
      09-24-2007
On Sep 22, 7:49 am, Weng Tianxiang <(E-Mail Removed)> wrote:
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>


It all depends on how you look at it; from a certain point of view,
the correct answer is one (1).

What you are calling state machines are just subordinate pieces of one
grand state machine.

G.

 
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