Handshake

I know this comes up often, but I have not been able to find a clear
solution so here goes:
I'm trying to implement a basic asynchronous handshake in VHDL, and
being relatively new to hardware synthesis, I'm having a great deal of
difficulty getting something that's glitch free.

1. A signal "read" is asserted externally.
2. On that rising edge, I would like to trigger a process that
calculates something and then outputs the result on the bus and then
asserts a "done" signal.
3. The assertion of "done" prompts the external system to read the
data and then drop the "read" signal.
4. The falling edge of "read" should start something that drops the
"done" signal, tristates the data output and generally resets
everything ready for another round.

This is all clockless from my point of view and should only be driven
by the read signal.

What I'm having a hard time getting my head around is a way to get the
"done" signal to be asserted as the result of the rising edge of
"read" and then deasserted as the result of a falling edge of "read".
In general I know this to be unsynthesizeable and generally frowned
upon, but at the same time, it's a common enough handshake method so
it must be doable. Right now I have a glitchy cludge that I'd like to
replace with "the right way of doing it".

Any thoughts? Can anyone show me some VHDL that does something similar
or a basic version of this?

As a bit of an extended question, how can I guarantee that "done"
comes on at exactly the same time or slightly after I place my data
on the bus (step 2. above)?

Thanks,

Chris Maryan

Chris Maryan

Chris Maryan wrote:

> I'm trying to implement a basic asynchronous handshake in VHDL, and
> being relatively new to hardware synthesis, I'm having a great deal of
> difficulty getting something that's glitch free.

> This is all clockless from my point of view and should only be driven
> by the read signal.

> Any thoughts? Can anyone show me some VHDL that does something similar
> or a basic version of this?

Add a clock and we'll talk.

-- Mike Treseler

Mike Treseler

On Sep 17, 11:17 am, Mike Treseler <mike_trese...@comcast.net> wrote:
> Add a clock and we'll talk.
>

And I'll second that. No sense trying to work this out
asyncronously. It's just the wrong way of doing it.

Add a clock

Shannon

Shannon

On Sep 17, 2:33 pm, Shannon <sgo...@sbcglobal.net> wrote:
> On Sep 17, 11:17 am, Mike Treseler <mike_trese...@comcast.net> wrote:
>
> > Add a clock and we'll talk.
>
> And I'll second that. No sense trying to work this out
> asyncronously. It's just the wrong way of doing it.
>
> Add a clock
>
> Shannon

That's fair. I've come up with a clocked solution, but was hoping my
attempt at doing this asynchronously would go somewhere.

Chris

Chris Maryan

>
> That's fair. I've come up with a clocked solution, but was hoping my
> attempt at doing this asynchronously would go somewhere.
>
> Chris

Unfortunatly, the "read" signal would be be similar to a "data_valid"
signal, which would have to be asserted after the data input is
stable. Then you would have to wait a finite time to allow the data
line to propogate through the circuit to allow that to become stable
before "done" is asserted. Without a clock this is impossible. You
could do this in VHDL with

if rising_edge(read) then
result <= transform(data) after N ns;
done <= '1' after N+M ns;
end if;

but this would not be synthesisable as all of the time delays are
ignored for synthesis.

Tricky