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doubt in vhdl

 
 
sreeram sreeram is offline
Junior Member
Join Date: Sep 2007
Posts: 2
 
      09-17-2007
I have a VHDL program, a package and a test bench. It works fine using Modelsim.But,I have a problem in using the Xilinx ISE8.2i version.

Main Program:

library ieee,work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.addmain.all;

entity add is
port (reset: in std_logic;
clock: in std_logic;
a : in addvector;
b : out std_logic_vector(7 downto 0)
);
end add;

architecture add_arch of add is
begin
process (reset,clock)
begin
if (reset='1')then
b <= '00000000';
else
if (clock'event and clock='1')then
b<= '0000' & ((a.operand1) + (a.operand2));
end if; -- For 'clock'
end if; -- For 'reset'
end process;
end add_arch;

Package Program:

library ieee;
use ieee.std_logic_1164.all;

package addmain is
type addvector is record
operand1: std_logic_vector (3 downto 0);
operand2: std_logic_vector (3 downto 0);
end record;
end addmain;

Test bench Program:

library ieee,work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.addmain.all;

entity testadd is
end testadd;

architecture testadd_arch of testadd is
signal tb_reset: std_logic;
signal tb_clock: std_logic;
signal tb_a : addvector;
signal tb_b : std_logic_vector (7 downto 0);

component add
port (reset: in std_logic;
clock: in std_logic;
a : in addvector;
b : out std_logic_vector(7 downto 0)
);
end component;
begin
UUT: add port map(reset=>tb_reset,
clock=>tb_clock,
a=>tb_a,
b=>tb_b);
clkrocess
begin
tb_clock <= '0';
wait for 50 ns;
tb_clock <= '1';
wait for 50 ns;
end process clk;

process
begin
tb_reset <= '1';
wait for 200 ns;
tb_reset <= '0';
tb_a.operand1 <= '0001';
tb_a.operand2 <= '0010';
wait for 400 ns;
tb_a.operand1 <= '0101';
tb_a.operand2 <= '0010';
wait for 400 ns;
wait;
end process;
end testadd_arch;

Now all my 3 files are working fine till post translate step. But when I try to go for the Post map stage some error comes…as below:

“# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Error: test-addmain.vhd(26): No default binding for component 'add'. (Port 'a' is not on the entity.)
# ** Warning: [1] (vopt-3473) Component instance 'uut : add' is not bound.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./testadd.mdo PAUSED at line 8”


Kindly reveal the solution for the above error if anyone is aware.
 
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