Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...

Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng

Weng Tianxiang

On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I would like to pose an interesting guess topics for experienced
> engineers:
> What is the largest number of state machines in a current chip design:
> 1k, 10k or ...
>
> I have finished 8 projects and only counted 27 state machines in one
> of my biggest designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.
>
> Weng


I am afraid as it stands your question does not make any sense.

These state machines:
1. How many states does each has?
2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work
questionable. Maybe you could live with a smaller number of FSMs. I
just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias

Uncle Noah

On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
> On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > Hi,
> > I would like to pose an interesting guess topics for experienced
> > engineers:
> > What is the largest number of state machines in a current chip design:
> > 1k, 10k or ...
>
> > I have finished 8 projects and only counted 27 state machines in one
> > of my biggest designs.
>
> > I may know the answer. The final result may surprise everyone who
> > gives a guess.
>
> > Weng
>
> I am afraid as it stands your question does not make any sense.
>
> These state machines:
> 1. How many states does each has?
> 2. State encoding, any associated datapath, operation?
>
> BTW 27 is not a small number but the quality of your work
> questionable. Maybe you could live with a smaller number of FSMs. I
> just say that 27 doesn't say anything. 42 either ^_^
>
> Nikolaos Kavvadias

Hi NK,
The guess is about what the largest number of state machine a current
chip may contain is.

It doesn't ask how many states each state machine has or what coding
method is used.

Just guess the largest number of state machine in a current chip
design.

It is not an easy guess, because your experiences may fall short of
imagination.

Why I listed 27 state machines is I used to make a wrong guessing
about the number, only based on my experiences with digital designs. I
guess most of experienced engineers may have the same experiences as I
had.

Weng

Weng Tianxiang

On Sep 17, 1:55 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
>
>
>
> > On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > I would like to pose an interesting guess topics for experienced
> > > engineers:
> > > What is the largest number of state machines in a current chip design:
> > > 1k, 10k or ...
>
> > > I have finished 8 projects and only counted 27 state machines in one
> > > of my biggest designs.
>
> > > I may know the answer. The final result may surprise everyone who
> > > gives a guess.
>
> > > Weng
>
> > I am afraid as it stands your question does not make any sense.
>
> > These state machines:
> > 1. How many states does each has?
> > 2. State encoding, any associated datapath, operation?
>
> > BTW 27 is not a small number but the quality of your work
> > questionable. Maybe you could live with a smaller number of FSMs. I
> > just say that 27 doesn't say anything. 42 either ^_^
>
> > Nikolaos Kavvadias
>
> Hi NK,
> The guess is about what the largest number of state machine a current
> chip may contain is.
>
> It doesn't ask how many states each state machine has or what coding
> method is used.
>
> Just guess the largest number of state machine in a current chip
> design.
>
> It is not an easy guess, because your experiences may fall short of
> imagination.
>
> Why I listed 27 state machines is I used to make a wrong guessing
> about the number, only based on my experiences with digital designs. I
> guess most of experienced engineers may have the same experiences as I
> had.
>
> Weng

The most state machines any design can have is the same as the number
of registers available on the design. Each register could be counted
as a 2 state FSM. so in todays FPGAs, there are is a maximum of
somewhere in the hundreds of thousands of FSMs.

Tricky

"Weng Tianxiang" <> wrote in message
news: ups.com...
>
> Weng
>

IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
this_could_go_on_all_week;
ANDIF both_the_above THEN
make_that_a_month;
BUTIF plonk! THEN
blessed_relief;
ELSIF experiences < imagination THEN
OP_question <= not(sense);
ELSE
possibly_on_topic;
END IF;

HTH., Syms.

p.s. Sorry, couldn't resist it!

p.p.s. I guess one. You can view the whole FPGA as one big state machine. Do
I win £5?

Symon

Hi,
I don't say how many state machines a design CAN or MAY generate, but
I say GUESS what the largest number of state machines a real design
ACTUALLY HAS GENERATED and those state machines are critical, not
trivial in design functions.

The problem core is how you know other people's design internal
affairs?

You may not have a chance to generate so many state machines and you
may not have the knowledge about why there are so many state
machines.

I guess less than 27 engineers in the world who have a chance to do
the designs and have the experiences.

All who have responded to the post so far seem to be no knowledge
about it and just missed the target.

Weng

Weng Tianxiang

Weng Tianxiang wrote:
> I would like to pose an interesting guess topics for experienced
> engineers:
> What is the largest number of state machines in a current chip design:
> 1k, 10k or ...
>
> I have finished 8 projects and only counted 27 state machines in one
> of my biggest designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.

As others have said, how do you define a state machine? Is an SRAM bit a state
machine? They fit quite a few of them onto a chip these days...

(followups set to remove crosspost)

--
Philip Potter pgp <at> doc.ic.ac.uk

Philip Potter

Hi,
OK, a state machine is defined by standard one process or two
processes in VHDL.

There is no short cut.

It can be implemented in anywhere in a design and where the state
machine is located is decided by compilers and beyond the interest of
this topics.

I have to expand the guess to include Verilog group people, because
VHDL people may have no chance to do the designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Thank you.

Weng

Weng Tianxiang

On Sep 17, 11:03 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> OK, a state machine is defined by standard one process or two
> processes in VHDL.
>
> There is no short cut.
>
> It can be implemented in anywhere in a design and where the state
> machine is located is decided by compilers and beyond the interest of
> this topics.
>
> I have to expand the guess to include Verilog group people, because
> VHDL people may have no chance to do the designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.
>
> Thank you.
>
> Weng

Ok Weng,

Since you obviously don't understand the questions the people who have
responded...

let's define a state machine as a process or processes that have a
classic "state variable". Sigh...
Furthermore since you rejected the concept that our guess should not
be based on what is "possible" but instead on what has actually been
done...

I will answer you question that ***I*** have created the design that
has the most classic state machines in it. And since you know the
answer you will tell ***me** how many I had to use. Hint: It's more
than 27 and I know you ***will*** be surprised by the answer!

Shannon

Shannon

On Sep 17, 11:14 am, Shannon <sgo...@sbcglobal.net> wrote:
> On Sep 17, 11:03 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
> > OK, a state machine is defined by standard one process or two
> > processes in VHDL.
>
> > There is no short cut.
>
> > It can be implemented in anywhere in a design and where the state
> > machine is located is decided by compilers and beyond the interest of
> > this topics.
>
> > I have to expand the guess to include Verilog group people, because
> > VHDL people may have no chance to do the designs.
>
> > I may know the answer. The final result may surprise everyone who
> > gives a guess.
>
> > Thank you.
>
> > Weng
>
> Ok Weng,
>
> Since you obviously don't understand the questions the people who have
> responded...
>
> let's define a state machine as a process or processes that have a
> classic "state variable". Sigh...
> Furthermore since you rejected the concept that our guess should not
> be based on what is "possible" but instead on what has actually been
> done...
>
> I will answer you question that ***I*** have created the design that
> has the most classic state machines in it. And since you know the
> answer you will tell ***me** how many I had to use. Hint: It's more
> than 27 and I know you ***will*** be surprised by the answer!
>
> Shannon- Hide quoted text -
>
> - Show quoted text -

Hi Shannon,
"let's define a state machine as a process or processes that have a
classic "state variable". Sigh... "

I don't write code for them, but you can expect how people in VHDL
define a state machine: by using type (...) as I like to do, but not
necessarily.

I cannot guess the largest number of state machines you have written
for a design, but I know clearly the number of state machines you may
have written in a design is less than 100k. Any question?

Weng

Weng Tianxiang