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problem with VHDL 93 style file_open

 
 
skiggeboi skiggeboi is offline
Junior Member
Join Date: Sep 2007
Location: Finland
Posts: 1
 
      09-13-2007
Hi,

Is it possible to open a file inside a VHDL process let say like this:
...
...
architecture problem of io is
begin
process (clk, reset_ax, manual_reset) is
-- file declarations
file dataout :text;
variable v : integer;
variable buf: line; -- buffer to file
variable fstatus: FILE_OPEN_STATUS;
begin
if(reset_ax, manual_reset) then
--reset some signals here
..
file_open(fstatus,dataout,"mytext.txt",write_mode) ; -- open the file
elsif(rising_edge(clk)
..
..
if(pulse is valid then write value to a file) then
v:= put valid value to v;
write(buf,v);
writeline(dataout,buf);
end if;

if(when all samples collected) then
file_close(dataout);
end if;
end if;
end process;
..
..
My problem is that I want to reset this file writing in some point(don't ask why =)) and start writing new samples to empty file(overwrite the old file).But it seems that after manual_reset signal, file is opened but it's in append_mode - so it continues to write end of this "old" file. I wonder why ? I have understood that opening the file in write_mode clears the "old" file and starts to write on a empty file...
I'm using Modelsim 6.1 and operating system is Unix.
Does anybody knows what I am missing here ? Appreciating any help..

-Skiggeboi-
 
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