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VHDL - overloading 'operators in VHDL |
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09-13-2007, 10:05 AM
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#1 |
overloading 'operators in VHDL
Hello,
I know that it is possible to overload operators like 'and', 'or', '+',... by using a function with the name "and", "or", "+",... . Is it also possible to overload the attribute operators like: 'high, 'left, 'low, ..? Is it possible to create your own attributes? best regards, Karel Dolphin |
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09-13-2007, 02:33 PM
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#2 |
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Posts: n/a
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Re: overloading 'operators in VHDL
On Sep 13, 4:05 am, Dolphin <Karel.Dep...@gemidis.be> wrote:
> Hello, > > I know that it is possible to overload operators like 'and', 'or', > '+',... by using a function with the name "and", "or", "+",... . > Is it also possible to overload the attribute operators like: 'high, > 'left, 'low, ..? Is it possible to create your own attributes? > > best regards, > Karel Yes, you can create your own attributes. No, you cannot overload the definition of existing attributes. I seem to recall that user-defined attributes are not passed with the argument that owns them into subprograms. Andy Andy |
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