«

[tonyfai]

Hi all! I am new to VHDL, and I am having a lot of trouble with it. Could all of the experts out there please help me with this problem?

I need a counter to synchronize the write and read operation for a image memory device. The counter needs to be reseted every time the signal OE triggers, both H to L and L to H. I wrote something like this:

COUNTER: PROCESS(OE,CLK)
variable counter : INTEGER RANGE 0 TO 60000;
BEGIN
IF (OE'EVENT) THEN
counter := 60000;
ELSIF (CLK'EVENT AND CLK= '1') THEN
counter := counter - 1;
END IF;

IF ( (counter < 60000) AND (counter > 57000) ) THEN
signal1 <= '1';
ELSE
signal1 <= '0';
END IF;

IF ( (counter < 3000) AND (counter > 0) ) THEN
signal2 <= '1';
ELSE
signal2 <= '0';
END IF;

END PROCESS COUNTER;

When I tried to compiled, Quartus will complain: Error (10633): VHDL Case Statement or If Statement error at Control.vhd(141): can't synthesize condition that contains an isolated 'EVENT predefined attribute

Is it possible to have the counter to depend on two signals, ie CLK and OE? If not, what can I do?

Thank you for your advices in advance!