![]() |
|
|
|||||||
![]() |
VHDL - Using packages in a hierarchical design |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
Don't you just love all these softball questions from me?
Ok, I did my search through comp.lang.vhdl and didn't find what I'm looking for. I'm using my own package in some of my lower-level modules (entity/ architecture pairs). When I stitch everything together in my top-level module then Quartus complains that I've got the package defined in more than one location. Ok, I comment out the lower-level ones and everything is fine. However, now when I edit my lower-level modules I have to keep uncomment/re-comment the package definition. There has GOT to be an easier (and more correct) method. Is there a way to "compile" the package separately so that I only have to "USE work.mypkg.all" in each of my lower-level modules? Shannon |
|
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Error: Physical sythesis tool PALAC is not supported by Formal Verification tool Conf | bbiandov | Software | 0 | 12-22-2008 05:25 AM |
| Sewing, Embroidery & SignMaking Software.. | embsupply | Software | 0 | 10-02-2007 04:29 PM |
| Sewing, Embroidery & SignMaking Software.. | embsupply | Software | 0 | 08-14-2007 04:01 PM |
| network design help....... | bunty4u | The Lounge | 1 | 04-08-2007 04:39 AM |
| Re: Reference Material On Server Chassis Design? | AG | A+ Certification | 0 | 01-30-2004 06:12 PM |