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VHDL - Using packages in a hierarchical design

 
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Old 09-11-2007, 05:43 AM   #1
Default Using packages in a hierarchical design


Don't you just love all these softball questions from me?

Ok, I did my search through comp.lang.vhdl and didn't find what I'm
looking for.

I'm using my own package in some of my lower-level modules (entity/
architecture pairs).
When I stitch everything together in my top-level module then Quartus
complains that I've got the package defined in more than one
location. Ok, I comment out the lower-level ones and everything is
fine.

However, now when I edit my lower-level modules I have to keep
uncomment/re-comment the package definition. There has GOT to be an
easier (and more correct) method.

Is there a way to "compile" the package separately so that I only have
to "USE work.mypkg.all" in each of my lower-level modules?



Shannon
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