1/2 Convolutional Encoder

Does anyone know how to implement a 1/2 (1 binary bit in, 2 out,
message length of 7) convolutional encoder in HDL? I am trying to
perform encoding on CNAV data, and am unsure of where the taps and
initial state value for the shift register is. Thanks.

mits130

On 10 Sep, 18:30, mits130 <amitpatel...@gmail.com> wrote:
> Does anyone know how to implement a 1/2 (1 binary bit in, 2 out,
> message length of 7) convolutional encoder in HDL? I am trying to
> perform encoding on CNAV data, and am unsure of where the taps and
> initial state value for the shift register is. Thanks.

I believe Xilinx offer one in their Coregen library, as well as a
Viterbi decoder.
But you obviously need to be using a Xilinx part.

KP.

Niv